From patchwork Sun Jul 10 18:14:44 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Avi Kivity X-Patchwork-Id: 104070 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id DCED5B70D1 for ; Mon, 11 Jul 2011 04:30:59 +1000 (EST) Received: from localhost ([::1]:48369 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QfymO-0007c4-FE for incoming@patchwork.ozlabs.org; Sun, 10 Jul 2011 14:30:56 -0400 Received: from eggs.gnu.org ([140.186.70.92]:46986) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QfyXQ-0004Gv-Up for qemu-devel@nongnu.org; Sun, 10 Jul 2011 14:15:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QfyXI-0007bB-Vw for qemu-devel@nongnu.org; Sun, 10 Jul 2011 14:15:26 -0400 Received: from mx1.redhat.com ([209.132.183.28]:31421) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QfyXD-0007Wn-WD for qemu-devel@nongnu.org; Sun, 10 Jul 2011 14:15:16 -0400 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p6AIFFgO005332 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Sun, 10 Jul 2011 14:15:15 -0400 Received: from cleopatra.tlv.redhat.com (cleopatra.tlv.redhat.com [10.35.255.11]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id p6AIFDjT032728; Sun, 10 Jul 2011 14:15:14 -0400 Received: from s01.tlv.redhat.com (s01.tlv.redhat.com [10.35.255.8]) by cleopatra.tlv.redhat.com (Postfix) with ESMTP id 72D98250B4E; Sun, 10 Jul 2011 21:15:11 +0300 (IDT) From: Avi Kivity To: qemu-devel@nongnu.org Date: Sun, 10 Jul 2011 21:14:44 +0300 Message-Id: <1310321709-30770-32-git-send-email-avi@redhat.com> In-Reply-To: <1310321709-30770-1-git-send-email-avi@redhat.com> References: <1310321709-30770-1-git-send-email-avi@redhat.com> X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.132.183.28 Cc: kvm@vger.kernel.org Subject: [Qemu-devel] [RFC v3 31/56] ac97: convert to memory API X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org fixes BAR sizing as well. Signed-off-by: Avi Kivity --- hw/ac97.c | 126 ++++++++++++++++++++++++++++++++++++++++++------------------ 1 files changed, 88 insertions(+), 38 deletions(-) diff --git a/hw/ac97.c b/hw/ac97.c index 0b59896..72a0667 100644 --- a/hw/ac97.c +++ b/hw/ac97.c @@ -160,8 +160,9 @@ typedef struct AC97LinkState { SWVoiceIn *voice_mc; int invalid_freq[3]; uint8_t silence[128]; - uint32_t base[2]; int bup_flag; + MemoryRegion io_nam; + MemoryRegion io_nabm; } AC97LinkState; enum { @@ -583,7 +584,7 @@ static uint32_t nam_readw (void *opaque, uint32_t addr) { AC97LinkState *s = opaque; uint32_t val = ~0U; - uint32_t index = addr - s->base[0]; + uint32_t index = addr; s->cas = 0; val = mixer_load (s, index); return val; @@ -611,7 +612,7 @@ static void nam_writeb (void *opaque, uint32_t addr, uint32_t val) static void nam_writew (void *opaque, uint32_t addr, uint32_t val) { AC97LinkState *s = opaque; - uint32_t index = addr - s->base[0]; + uint32_t index = addr; s->cas = 0; switch (index) { case AC97_Reset: @@ -706,6 +707,37 @@ static void nam_writel (void *opaque, uint32_t addr, uint32_t val) s->cas = 0; } +static uint64_t nam_read(void *opaque, target_phys_addr_t addr, unsigned size) +{ + AC97LinkState *s = opaque; + + switch (size) { + case 1: return nam_readb(s, addr); + case 2: return nam_readw(s, addr); + case 4: return nam_readl(s, addr); + default: abort(); + } +} + +static void nam_write(void *opaque, target_phys_addr_t addr, + uint64_t data, unsigned size) +{ + AC97LinkState *s = opaque; + + switch (size) { + case 1: return nam_writeb(s, addr, data); + case 2: return nam_writew(s, addr, data); + case 4: return nam_writel(s, addr, data); + default: abort(); + } +} + +static MemoryRegionOps ac97_io_nam_ops = { + .read = nam_read, + .write = nam_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + /** * Native audio bus master * I/O Reads @@ -714,7 +746,7 @@ static uint32_t nabm_readb (void *opaque, uint32_t addr) { AC97LinkState *s = opaque; AC97BusMasterRegs *r = NULL; - uint32_t index = addr - s->base[1]; + uint32_t index = addr; uint32_t val = ~0U; switch (index) { @@ -769,7 +801,7 @@ static uint32_t nabm_readw (void *opaque, uint32_t addr) { AC97LinkState *s = opaque; AC97BusMasterRegs *r = NULL; - uint32_t index = addr - s->base[1]; + uint32_t index = addr; uint32_t val = ~0U; switch (index) { @@ -798,7 +830,7 @@ static uint32_t nabm_readl (void *opaque, uint32_t addr) { AC97LinkState *s = opaque; AC97BusMasterRegs *r = NULL; - uint32_t index = addr - s->base[1]; + uint32_t index = addr; uint32_t val = ~0U; switch (index) { @@ -848,7 +880,7 @@ static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val) { AC97LinkState *s = opaque; AC97BusMasterRegs *r = NULL; - uint32_t index = addr - s->base[1]; + uint32_t index = addr; switch (index) { case PI_LVI: case PO_LVI: @@ -904,7 +936,7 @@ static void nabm_writew (void *opaque, uint32_t addr, uint32_t val) { AC97LinkState *s = opaque; AC97BusMasterRegs *r = NULL; - uint32_t index = addr - s->base[1]; + uint32_t index = addr; switch (index) { case PI_SR: case PO_SR: @@ -924,7 +956,7 @@ static void nabm_writel (void *opaque, uint32_t addr, uint32_t val) { AC97LinkState *s = opaque; AC97BusMasterRegs *r = NULL; - uint32_t index = addr - s->base[1]; + uint32_t index = addr; switch (index) { case PI_BDBAR: case PO_BDBAR: @@ -954,6 +986,38 @@ static void nabm_writel (void *opaque, uint32_t addr, uint32_t val) } } +static uint64_t nabm_read(void *opaque, target_phys_addr_t addr, + unsigned size) +{ + AC97LinkState *s = opaque; + + switch (size) { + case 1: return nabm_readb(s, addr); + case 2: return nabm_readw(s, addr); + case 4: return nabm_readl(s, addr); + default: abort(); + } +} + +static void nabm_write(void *opaque, target_phys_addr_t addr, + uint64_t data, unsigned size) +{ + AC97LinkState *s = opaque; + + switch (size) { + case 1: return nabm_writeb(s, addr, data); + case 2: return nabm_writew(s, addr, data); + case 4: return nabm_writel(s, addr, data); + default: abort(); + } +} + +static MemoryRegionOps ac97_io_nabm_ops = { + .read = nabm_read, + .write = nabm_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + static int write_audio (AC97LinkState *s, AC97BusMasterRegs *r, int max, int *stop) { @@ -1230,32 +1294,6 @@ static const VMStateDescription vmstate_ac97 = { } }; -static void ac97_map (PCIDevice *pci_dev, int region_num, - pcibus_t addr, pcibus_t size, int type) -{ - AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, pci_dev); - PCIDevice *d = &s->dev; - - if (!region_num) { - s->base[0] = addr; - register_ioport_read (addr, 256 * 1, 1, nam_readb, d); - register_ioport_read (addr, 256 * 2, 2, nam_readw, d); - register_ioport_read (addr, 256 * 4, 4, nam_readl, d); - register_ioport_write (addr, 256 * 1, 1, nam_writeb, d); - register_ioport_write (addr, 256 * 2, 2, nam_writew, d); - register_ioport_write (addr, 256 * 4, 4, nam_writel, d); - } - else { - s->base[1] = addr; - register_ioport_read (addr, 64 * 1, 1, nabm_readb, d); - register_ioport_read (addr, 64 * 2, 2, nabm_readw, d); - register_ioport_read (addr, 64 * 4, 4, nabm_readl, d); - register_ioport_write (addr, 64 * 1, 1, nabm_writeb, d); - register_ioport_write (addr, 64 * 2, 2, nabm_writew, d); - register_ioport_write (addr, 64 * 4, 4, nabm_writel, d); - } -} - static void ac97_on_reset (void *opaque) { AC97LinkState *s = opaque; @@ -1311,15 +1349,26 @@ static int ac97_initfn (PCIDevice *dev) /* TODO: RST# value should be 0. */ c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */ - pci_register_bar (&s->dev, 0, 256 * 4, PCI_BASE_ADDRESS_SPACE_IO, - ac97_map); - pci_register_bar (&s->dev, 1, 64 * 4, PCI_BASE_ADDRESS_SPACE_IO, ac97_map); + memory_region_init_io(&s->io_nam, &ac97_io_nam_ops, s, "ac97-nam", 1024); + memory_region_init_io(&s->io_nabm, &ac97_io_nabm_ops, s, "ac97-nabm", 256); + + pci_register_bar_region(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam); + pci_register_bar_region(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm); qemu_register_reset (ac97_on_reset, s); AUD_register_card ("ac97", &s->card); ac97_on_reset (s); return 0; } +static int ac97_exitfn(PCIDevice *dev) +{ + AC97LinkState *s = DO_UPCAST(AC97LinkState, dev, dev); + + memory_region_destroy(&s->io_nam); + memory_region_destroy(&s->io_nabm); + return 0; +} + int ac97_init (PCIBus *bus) { pci_create_simple (bus, -1, "AC97"); @@ -1332,6 +1381,7 @@ static PCIDeviceInfo ac97_info = { .qdev.size = sizeof (AC97LinkState), .qdev.vmsd = &vmstate_ac97, .init = ac97_initfn, + .exit = ac97_exitfn, .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801AA_5, .revision = 0x01,