From patchwork Mon Feb 11 22:13:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukas Auer X-Patchwork-Id: 1040178 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aisec.fraunhofer.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43z0Xv44Lpz9sCh for ; Tue, 12 Feb 2019 09:18:07 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 46119C22070; Mon, 11 Feb 2019 22:15:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C7106C22092; Mon, 11 Feb 2019 22:14:46 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5364AC2206E; Mon, 11 Feb 2019 22:14:36 +0000 (UTC) Received: from mail-edgeS23.fraunhofer.de (mail-edges23.fraunhofer.de [153.97.7.23]) by lists.denx.de (Postfix) with ESMTPS id 389FFC22070 for ; Mon, 11 Feb 2019 22:14:32 +0000 (UTC) X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A2FbAAAO4PJb/xmnZsBiGgEBAQEBAgEBAQEHAgEBAQGBZYIEgVY5jG+LHZs9DYRsAoNuIjgSAQMBAQIBAQICAmkohT4GMgFGEFE9GgYOBYMhggKofIocCQGHUIQrgVc/gRGIXYUOAosIlGcHAoERgQkEjn4LGIlYhyWYFoFdIoFVMxokgzuQWz4BMgGOWwEB X-IPAS-Result: A2FbAAAO4PJb/xmnZsBiGgEBAQEBAgEBAQEHAgEBAQGBZYIEgVY5jG+LHZs9DYRsAoNuIjgSAQMBAQIBAQICAmkohT4GMgFGEFE9GgYOBYMhggKofIocCQGHUIQrgVc/gRGIXYUOAosIlGcHAoERgQkEjn4LGIlYhyWYFoFdIoFVMxokgzuQWz4BMgGOWwEB X-IronPort-AV: E=Sophos;i="5.56,253,1539640800"; d="scan'208";a="9182861" Received: from mail-mtadd25.fraunhofer.de ([192.102.167.25]) by mail-edgeS23.fraunhofer.de with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Feb 2019 23:14:31 +0100 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A0DkAAAq4PJb/xBhWMBiGwEBAQEDAQEBBwMBAQGBZYM5ITmMb6ZaDYRsAoQPOBIBAwEBAgEBAm0ohT0GMgFGEFE9GgYOBYMhggKofIodCQGHUIYCP4ERiF2FDgKLCJRnBwKBEYEJBI5+CxiJWIclmBaBXSGBVTMaJIM7kFs+AzABjlsBAQ X-IronPort-AV: E=Sophos;i="5.56,253,1539640800"; d="scan'208";a="31721293" Received: from fgdemucivp01ltm.xch.fraunhofer.de (HELO FGDEMUCIMP11EXC.ads.fraunhofer.de) ([192.88.97.16]) by mail-mtaDD25.fraunhofer.de with ESMTP/TLS/AES256-SHA; 11 Feb 2019 23:14:31 +0100 Received: from localhost.de (10.80.233.50) by FGDEMUCIMP11EXC.ads.fraunhofer.de (10.80.232.42) with Microsoft SMTP Server (TLS) id 14.3.435.0; Mon, 11 Feb 2019 23:16:21 +0100 From: Lukas Auer To: Date: Mon, 11 Feb 2019 23:13:41 +0100 Message-ID: <20190211221345.31980-5-lukas.auer@aisec.fraunhofer.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190211221345.31980-1-lukas.auer@aisec.fraunhofer.de> References: <20190211221345.31980-1-lukas.auer@aisec.fraunhofer.de> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.4179-8.200.1013-24422.005 X-TM-AS-Result: No-0.061700-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No Cc: Palmer Dabbelt , Andreas Schwab , Alexander Graf Subject: [U-Boot] [PATCH 4/7] riscv: delay initialization of caches and debug UART X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Move the initialization of the caches and the debug UART until after board_init_f_init_reserve. This is in preparation for SMP support, where code prior to this point will be executed by all harts. This ensures that initialization will only be performed once for the main hart running U-Boot. Signed-off-by: Lukas Auer Reviewed-by: Anup Patel Reviewed-by: Bin Meng --- arch/riscv/cpu/start.S | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 81ea52b170..a30f6f7194 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -45,10 +45,6 @@ _start: /* mask all interrupts */ csrw MODE_PREFIX(ie), zero - /* Enable cache */ - jal icache_enable - jal dcache_enable - /* * Set stackpointer in internal/ex RAM to call board_init_f */ @@ -57,10 +53,6 @@ call_board_init_f: li t1, CONFIG_SYS_INIT_SP_ADDR and sp, t1, t0 /* force 16 byte alignment */ -#ifdef CONFIG_DEBUG_UART - jal debug_uart_init -#endif - call_board_init_f_0: mv a0, sp jal board_init_f_alloc_reserve @@ -74,6 +66,14 @@ call_board_init_f_0: /* save the boot hart id to global_data */ SREG s0, GD_BOOT_HART(gp) + /* Enable cache */ + jal icache_enable + jal dcache_enable + +#ifdef CONFIG_DEBUG_UART + jal debug_uart_init +#endif + mv a0, zero /* a0 <-- boot_flags = 0 */ la t5, board_init_f jr t5 /* jump to board_init_f() */