[U-Boot,3/7] riscv: implement IPI platform functions using SBI

Message ID 20190211221345.31980-4-lukas.auer@aisec.fraunhofer.de
State Superseded
Delegated to: Andes
Headers show
Series
  • SMP support for RISC-V
Related show

Commit Message

Auer, Lukas Feb. 11, 2019, 10:13 p.m.
The supervisor binary interface (SBI) provides the necessary functions
to implement the platform IPI functions riscv_send_ipi() and
riscv_clear_ipi(). Use it to implement them.

This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs
running in supervisor mode. Support for machine mode is already
available for CPUs that include the SiFive CLINT.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
---

 arch/riscv/Kconfig       |  5 +++++
 arch/riscv/lib/Makefile  |  1 +
 arch/riscv/lib/sbi_ipi.c | 25 +++++++++++++++++++++++++
 3 files changed, 31 insertions(+)
 create mode 100644 arch/riscv/lib/sbi_ipi.c

Comments

Anup Patel Feb. 12, 2019, 2:32 a.m. | #1
> -----Original Message-----
> From: Lukas Auer [mailto:lukas.auer@aisec.fraunhofer.de]
> Sent: Tuesday, February 12, 2019 3:44 AM
> To: u-boot@lists.denx.de
> Cc: Atish Patra <Atish.Patra@wdc.com>; Anup Patel
> <Anup.Patel@wdc.com>; Bin Meng <bmeng.cn@gmail.com>; Andreas
> Schwab <schwab@suse.de>; Palmer Dabbelt <palmer@sifive.com>;
> Alexander Graf <agraf@suse.de>; Lukas Auer
> <lukas.auer@aisec.fraunhofer.de>; Anup Patel <anup@brainfault.org>; Rick
> Chen <rick@andestech.com>
> Subject: [PATCH 3/7] riscv: implement IPI platform functions using SBI
> 
> The supervisor binary interface (SBI) provides the necessary functions to
> implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi().
> Use it to implement them.
> 
> This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs
> running in supervisor mode. Support for machine mode is already available
> for CPUs that include the SiFive CLINT.
> 
> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> ---
> 
>  arch/riscv/Kconfig       |  5 +++++
>  arch/riscv/lib/Makefile  |  1 +
>  arch/riscv/lib/sbi_ipi.c | 25 +++++++++++++++++++++++++
>  3 files changed, 31 insertions(+)
>  create mode 100644 arch/riscv/lib/sbi_ipi.c
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index
> c0842178dd..3a51339c4d 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -135,4 +135,9 @@ config NR_CPUS
>  	  Stack memory is pre-allocated. U-Boot must therefore know the
>  	  maximum number of CPUs that may be present.
> 
> +config SBI_IPI
> +	bool
> +	default y if RISCV_SMODE
> +	depends on SMP
> +
>  endmenu
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index
> 19370f9749..35dbf643e4 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -13,6 +13,7 @@ obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
>  obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
>  obj-y	+= interrupts.o
>  obj-y	+= reset.o
> +obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
>  obj-y   += setjmp.o
>  obj-$(CONFIG_SMP) += smp.o
> 
> diff --git a/arch/riscv/lib/sbi_ipi.c b/arch/riscv/lib/sbi_ipi.c new file mode
> 100644 index 0000000000..170346da68
> --- /dev/null
> +++ b/arch/riscv/lib/sbi_ipi.c
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Fraunhofer AISEC,
> + * Lukas Auer <lukas.auer@aisec.fraunhofer.de>  */
> +
> +#include <common.h>
> +#include <asm/sbi.h>
> +
> +int riscv_send_ipi(int hart)
> +{
> +	ulong mask;
> +
> +	mask = 1UL << hart;
> +	sbi_send_ipi(&mask);
> +
> +	return 0;
> +}
> +
> +int riscv_clear_ipi(int hart)
> +{
> +	sbi_clear_ipi();
> +
> +	return 0;
> +}
> --
> 2.20.1

Looks good to me.

Reviewed-by: Anup Patel <anup.patel@wdc.com>

Regards,
Anup
Bin Meng Feb. 12, 2019, 3:03 a.m. | #2
On Tue, Feb 12, 2019 at 6:14 AM Lukas Auer
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> The supervisor binary interface (SBI) provides the necessary functions
> to implement the platform IPI functions riscv_send_ipi() and
> riscv_clear_ipi(). Use it to implement them.
>
> This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs
> running in supervisor mode. Support for machine mode is already
> available for CPUs that include the SiFive CLINT.
>
> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> ---
>
>  arch/riscv/Kconfig       |  5 +++++
>  arch/riscv/lib/Makefile  |  1 +
>  arch/riscv/lib/sbi_ipi.c | 25 +++++++++++++++++++++++++
>  3 files changed, 31 insertions(+)
>  create mode 100644 arch/riscv/lib/sbi_ipi.c
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Patch

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index c0842178dd..3a51339c4d 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -135,4 +135,9 @@  config NR_CPUS
 	  Stack memory is pre-allocated. U-Boot must therefore know the
 	  maximum number of CPUs that may be present.
 
+config SBI_IPI
+	bool
+	default y if RISCV_SMODE
+	depends on SMP
+
 endmenu
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 19370f9749..35dbf643e4 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -13,6 +13,7 @@  obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
 obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
 obj-y	+= interrupts.o
 obj-y	+= reset.o
+obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
 obj-y   += setjmp.o
 obj-$(CONFIG_SMP) += smp.o
 
diff --git a/arch/riscv/lib/sbi_ipi.c b/arch/riscv/lib/sbi_ipi.c
new file mode 100644
index 0000000000..170346da68
--- /dev/null
+++ b/arch/riscv/lib/sbi_ipi.c
@@ -0,0 +1,25 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Fraunhofer AISEC,
+ * Lukas Auer <lukas.auer@aisec.fraunhofer.de>
+ */
+
+#include <common.h>
+#include <asm/sbi.h>
+
+int riscv_send_ipi(int hart)
+{
+	ulong mask;
+
+	mask = 1UL << hart;
+	sbi_send_ipi(&mask);
+
+	return 0;
+}
+
+int riscv_clear_ipi(int hart)
+{
+	sbi_clear_ipi();
+
+	return 0;
+}