[13/15] ARM: dts: imx6qdl-aristainetos: fix swpad values for reserved values

Message ID 20190211141333.28725-13-u.kleine-koenig@pengutronix.de
State New
Headers show
Series
  • [01/15] ARM: dts: imx6qdl-fdi-fs700-m60: Use explicit swpad values
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Commit Message

Uwe Kleine-König Feb. 11, 2019, 2:13 p.m.
The IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04 register reads back as 0 when
0x20000 was written to it because bit 17 is readonly. So change the
swpad value accordingly to not write a 1 to this reserved bit.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 arch/arm/boot/dts/imx6qdl-aristainetos.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Patch

diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
index ee4d0f84eeb2..4d2968850b75 100644
--- a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
@@ -328,7 +328,7 @@ 
 				MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0x10
 				MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02		0x10
 				MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03		0x10
-				MX6QDL_PAD_DI0_PIN4__GPIO4_IO20			0x20000
+				MX6QDL_PAD_DI0_PIN4__GPIO4_IO20			0x00
 				MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00	0x10
 				MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01	0x10
 				MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02	0x10