[net-next,2/2] net: marvell: mvpp2: use mvpp2_is_xlg() helper elsewhere

Message ID E1gt8k7-0007iN-I2@rmk-PC.armlinux.org.uk
State Accepted
Delegated to: David Miller
Headers show
Series
  • [net-next,1/2] net: marvell: mvpp2: add mvpp2_is_xlg() helper
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Commit Message

Russell King Feb. 11, 2019, 10:23 a.m.
There are several places which make the decision whether to access the
XLGMAC vs GMAC that only check for PHY_INTERFACE_MODE_10GKR and not its
XAUI variant.  Switch these to use the new helper so that we have
consistency through the driver.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

Comments

Maxime Chevallier Feb. 11, 2019, 11:02 a.m. | #1
Hello Russell,

On Mon, 11 Feb 2019 10:23:15 +0000
Russell King <rmk+kernel@armlinux.org.uk> wrote:

>There are several places which make the decision whether to access the
>XLGMAC vs GMAC that only check for PHY_INTERFACE_MODE_10GKR and not its
>XAUI variant.  Switch these to use the new helper so that we have
>consistency through the driver.
>
>Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>

Thanks,

Maxime
David Miller Feb. 12, 2019, 5:33 p.m. | #2
From: Russell King <rmk+kernel@armlinux.org.uk>
Date: Mon, 11 Feb 2019 10:23:15 +0000

> There are several places which make the decision whether to access the
> XLGMAC vs GMAC that only check for PHY_INTERFACE_MODE_10GKR and not its
> XAUI variant.  Switch these to use the new helper so that we have
> consistency through the driver.
> 
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

Applied.

Patch

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index 03c79618bfef..94c92a49f12f 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -1106,7 +1106,7 @@  static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
 	if (port->gop_id == 0) {
 		/* Enable the XLG/GIG irqs for this port */
 		val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
-		if (port->phy_interface == PHY_INTERFACE_MODE_10GKR)
+		if (mvpp2_is_xlg(port->phy_interface))
 			val |= MVPP22_XLG_EXT_INT_MASK_XLG;
 		else
 			val |= MVPP22_XLG_EXT_INT_MASK_GIG;
@@ -2471,8 +2471,7 @@  static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
 
 	mvpp22_gop_mask_irq(port);
 
-	if (port->gop_id == 0 &&
-	    port->phy_interface == PHY_INTERFACE_MODE_10GKR) {
+	if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) {
 		val = readl(port->base + MVPP22_XLG_INT_STAT);
 		if (val & MVPP22_XLG_INT_STAT_LINK) {
 			event = true;
@@ -4680,7 +4679,7 @@  static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
 	bool change_interface = port->phy_interface != state->interface;
 
 	/* Check for invalid configuration */
-	if (state->interface == PHY_INTERFACE_MODE_10GKR && port->gop_id != 0) {
+	if (mvpp2_is_xlg(state->interface) && port->gop_id != 0) {
 		netdev_err(dev, "Invalid mode on %s\n", dev->name);
 		return;
 	}
@@ -4700,7 +4699,7 @@  static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
 	}
 
 	/* mac (re)configuration */
-	if (state->interface == PHY_INTERFACE_MODE_10GKR)
+	if (mvpp2_is_xlg(state->interface))
 		mvpp2_xlg_config(port, mode, state);
 	else if (phy_interface_mode_is_rgmii(state->interface) ||
 		 phy_interface_mode_is_8023z(state->interface) ||
@@ -4722,8 +4721,7 @@  static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode,
 	struct mvpp2_port *port = netdev_priv(dev);
 	u32 val;
 
-	if (!phylink_autoneg_inband(mode) &&
-	    interface != PHY_INTERFACE_MODE_10GKR) {
+	if (!phylink_autoneg_inband(mode) && !mvpp2_is_xlg(interface)) {
 		val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
 		val &= ~MVPP2_GMAC_FORCE_LINK_DOWN;
 		val |= MVPP2_GMAC_FORCE_LINK_PASS;
@@ -4743,8 +4741,7 @@  static void mvpp2_mac_link_down(struct net_device *dev, unsigned int mode,
 	struct mvpp2_port *port = netdev_priv(dev);
 	u32 val;
 
-	if (!phylink_autoneg_inband(mode) &&
-	    interface != PHY_INTERFACE_MODE_10GKR) {
+	if (!phylink_autoneg_inband(mode) && !mvpp2_is_xlg(interface)) {
 		val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
 		val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
 		val |= MVPP2_GMAC_FORCE_LINK_DOWN;