Patchwork [net-next,1/5] igb: Fix lack of flush after register write and before delay

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Submitter Jeff Kirsher
Date July 9, 2011, 11:50 a.m.
Message ID <1310212240-24623-2-git-send-email-jeffrey.t.kirsher@intel.com>
Download mbox | patch
Permalink /patch/103972/
State Changes Requested
Delegated to: David Miller
Headers show

Comments

Jeff Kirsher - July 9, 2011, 11:50 a.m.
From: Carolyn Wyborny <carolyn.wyborny@intel.com>

Register writes followed by a delay are required to have a flush
before the delay in order to commit the values to the register.  Without
the flush, the code following the delay may not function correctly.

Reported-by: Tong Ho <tong.ho@ericsson.com>
Reported-by: Guenter Roeck <guenter.roeck@ericsson.com>
Signed-off-by: Carolyn Wyborny <carolyn.wyborny@intel.com>
Tested-by:  Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---
 drivers/net/igb/e1000_82575.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

Patch

diff --git a/drivers/net/igb/e1000_82575.c b/drivers/net/igb/e1000_82575.c
index 0f563c8..493e331 100644
--- a/drivers/net/igb/e1000_82575.c
+++ b/drivers/net/igb/e1000_82575.c
@@ -1735,6 +1735,7 @@  static s32 igb_reset_hw_82580(struct e1000_hw *hw)
 		ctrl |= E1000_CTRL_RST;
 
 	wr32(E1000_CTRL, ctrl);
+	wrfl();
 
 	/* Add delay to insure DEV_RST has time to complete */
 	if (global_device_reset)