From patchwork Mon Feb 11 06:59:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1039674 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="UjlkfnYL"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43ycGV33qZz9sML for ; Mon, 11 Feb 2019 18:04:18 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 25247C21FA8; Mon, 11 Feb 2019 07:02:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 135EBC2207D; Mon, 11 Feb 2019 07:00:34 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 33221C22074; Mon, 11 Feb 2019 07:00:25 +0000 (UTC) Received: from mail-pl1-f196.google.com (mail-pl1-f196.google.com [209.85.214.196]) by lists.denx.de (Postfix) with ESMTPS id 5B17FC22074 for ; Mon, 11 Feb 2019 07:00:22 +0000 (UTC) Received: by mail-pl1-f196.google.com with SMTP id g9so4890935plo.3 for ; Sun, 10 Feb 2019 23:00:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YG+P7iyhrmbReSHJuAEy81foRFGrHKTICs/m0yn8Wlg=; b=UjlkfnYL10cZstljNUiyOSk4Y8wg8RbdsStWDUvbquaaUpmB6vZN3HCyqPd/zDYSkB EVkiGhtMcyCaVCfsxbtXFXC/6zSRFG/YxUKR3uJZKXxvmJZDj4fvJyrE1CCEMwkjmDv7 7QRJ7BowvFzPU72SvhpqCzROkN4KuCXAI0yyc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YG+P7iyhrmbReSHJuAEy81foRFGrHKTICs/m0yn8Wlg=; b=sgR0AVEmG8L9/KhnftSqnD8+lZhU3qTXSyVZgGJnewnDs+iaWCBud/afNglxdRDlZm 3c0EYuE62EuPpWe/Prp7Vwy4bxbVyyTtSZJnL/rRHXijT5zmc0/U6ESrh/dLLVlRZsJf FbI1RmbMhvc5OeI/TulLVI92YEXegfwbDFeRGsJCG0BTIqcBVb3up/DdnBkzYz8N4VLA AvzY2z0bbx9w1Ub/0PVZ/SMYkxwAI90ETz+YsfxJ9P5kML6u81kROWpRZhB/DL4Nt7Of hsY4UD+w1ImwbVaPEdyJxRjQkeQB7tJ7K5PoiBsUc7+0v2DtE7ceOrTM0YN5dO8J59pS CMZw== X-Gm-Message-State: AHQUAuY2n2mhM4pMzdyPp5jpdusaEtpZZ7qviT8Kon6TTRe4/2jbodRZ ZhtMf+yZzjoWVPuzfhbPhoIR+w== X-Google-Smtp-Source: AHgI3Ia4hdlxDaVOTHKTVEwfl2NzRcMof/VxGVXy/NWFWZoB6xhuKy0uBnn1C6T2DMTufmCmPlV+bA== X-Received: by 2002:a17:902:50e3:: with SMTP id c32mr36158861plj.318.1549868420974; Sun, 10 Feb 2019 23:00:20 -0800 (PST) Received: from localhost.localdomain ([115.97.184.151]) by smtp.gmail.com with ESMTPSA id t3sm81529pga.31.2019.02.10.23.00.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 10 Feb 2019 23:00:20 -0800 (PST) From: Jagan Teki To: Maxime Ripard Date: Mon, 11 Feb 2019 12:29:36 +0530 Message-Id: <20190211065937.4875-13-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190211065937.4875-1-jagan@amarulasolutions.com> References: <20190211065937.4875-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Joe Hershberger Subject: [U-Boot] [PATCH v2 12/13] net: sun8i_emac: Add EPHY CLK and RESET support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger Cc: Lothar Felten Signed-off-by: Jagan Teki --- drivers/net/sun8i_emac.c | 72 ++++++++++++++++++++++++++++++---------- 1 file changed, 55 insertions(+), 17 deletions(-) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 98bd7a5823..28347cb543 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -138,7 +138,9 @@ struct emac_eth_dev { struct phy_device *phydev; struct mii_dev *bus; struct clk tx_clk; + struct clk ephy_clk; struct reset_ctl tx_rst; + struct reset_ctl ephy_rst; #ifdef CONFIG_DM_GPIO struct gpio_desc reset_gpio; #endif @@ -653,7 +655,6 @@ static int sun8i_eth_write_hwaddr(struct udevice *dev) static int sun8i_emac_board_setup(struct emac_eth_dev *priv) { - struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; int ret; ret = clk_enable(&priv->tx_clk); @@ -670,16 +671,20 @@ static int sun8i_emac_board_setup(struct emac_eth_dev *priv) } } - if (priv->variant == H3_EMAC) { - /* Only H3/H5 have clock controls for internal EPHY */ - if (priv->use_internal_phy) { - /* Set clock gating for ephy */ - setbits_le32(&ccm->bus_gate4, - BIT(AHB_GATE_OFFSET_EPHY)); - - /* Deassert EPHY */ - setbits_le32(&ccm->ahb_reset2_cfg, - BIT(AHB_RESET_OFFSET_EPHY)); + /* Only H3/H5 have clock controls for internal EPHY */ + if (clk_valid(&priv->ephy_clk)) { + ret = clk_enable(&priv->ephy_clk); + if (ret) { + dev_err(dev, "failed to enable EPHY TX clock\n"); + return ret; + } + } + + if (reset_valid(&priv->ephy_rst)) { + ret = reset_deassert(&priv->ephy_rst); + if (ret) { + dev_err(dev, "failed to deassert EPHY TX clock\n"); + return ret; } } @@ -839,6 +844,42 @@ static const struct eth_ops sun8i_emac_eth_ops = { .stop = sun8i_emac_eth_stop, }; +static int sun8i_get_ephy_nodes(struct emac_eth_dev *priv) +{ + int node, ret; + + /* look for mdio-mux node for internal PHY node */ + node = fdt_path_offset(gd->fdt_blob, + "/soc/ethernet@1c30000/mdio-mux/mdio@1/ethernet-phy@1"); + if (node < 0) { + debug("failed to get mdio-mux with internal PHY\n"); + return node; + } + + ret = fdt_node_check_compatible(gd->fdt_blob, node, + "allwinner,sun8i-h3-mdio-internal"); + if (ret < 0) { + debug("failed to find mdio-internal node\n"); + return ret; + } + + ret = clk_get_by_index_nodev(offset_to_ofnode(node), 0, &priv->ephy_clk); + if (ret) { + dev_err(dev, "failed to get EPHY TX clock\n"); + return ret; + } + + ret = reset_get_by_index_nodev(offset_to_ofnode(node), 0, &priv->ephy_rst); + if (ret) { + dev_err(dev, "failed to get EPHY TX reset\n"); + return ret; + } + + priv->use_internal_phy = true; + + return 0; +} + static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) { struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev); @@ -920,12 +961,9 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) } if (priv->variant == H3_EMAC) { - int parent = fdt_parent_offset(gd->fdt_blob, offset); - - if (parent >= 0 && - !fdt_node_check_compatible(gd->fdt_blob, parent, - "allwinner,sun8i-h3-mdio-internal")) - priv->use_internal_phy = true; + ret = sun8i_get_ephy_nodes(priv); + if (ret) + return ret; } priv->interface = pdata->phy_interface;