From patchwork Sat Feb 9 13:14:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1039188 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="osGrrVfj"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43xXjW2qnBz9sMl for ; Sun, 10 Feb 2019 00:20:31 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id BE32AC21F97; Sat, 9 Feb 2019 13:18:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B47F5C2204D; Sat, 9 Feb 2019 13:16:01 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B2166C21FE0; Sat, 9 Feb 2019 13:15:30 +0000 (UTC) Received: from mail-pf1-f196.google.com (mail-pf1-f196.google.com [209.85.210.196]) by lists.denx.de (Postfix) with ESMTPS id BDF1DC21FCF for ; Sat, 9 Feb 2019 13:15:25 +0000 (UTC) Received: by mail-pf1-f196.google.com with SMTP id j3so2974707pfi.12 for ; Sat, 09 Feb 2019 05:15:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mYSW22DKyaUZGsX9BxuIz+RrPPMHAV1p0E9BZd7fyvI=; b=osGrrVfj/8aCsXewudT4/6o7+rtuskEHg0GMWoXeTuPHSLkO7UcMH3iKBl3fQdm38K Skj5dim9jFkdQZbSDCWvIhpDraRMvAf63kU/MigfTcAsgnW1QLcP4swufQXe43koJmwC Dt+eJLvm2JdDb4b1iKhFWh1lTXOuSf9VeWl6A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mYSW22DKyaUZGsX9BxuIz+RrPPMHAV1p0E9BZd7fyvI=; b=tehYykwNegN6uED7LEauiDiTSSqT9fs9tiMfg4Duxkai9omn0DU5bcp3sCHmx3hYLe B8msgUgDgETqGdaAP7pjC9I7/q0I7PTjKjmThLt6J0blX4TVgoX9d16MeEfwJsKI/H33 6AVUaTkrFMS/JFbX4GkyX9D59UsHkj5qSUj6ntvliK/7idHmhsX4w4LCgr/Y+gdZBZpF zp8KNwcjFi0uAULV5TgNXtEtYHKQXCKDkFCACPntLrKR5+Zfv0bdkfdxbq8BSyVUu1Xk gHLC6aCldzydsRbI15Ez0WSvfzm8ccorU24IG+dmi/XRyPfb8huoSeVy32UOJGhbJM2b TvNg== X-Gm-Message-State: AHQUAuZCvRLxqOCNnLNmVF5sSh3H6uSOXOSW8HUBMX8bZKYcN0BerEy+ HxMTZF6DcQl6kt+wE0l9hTvT9Q== X-Google-Smtp-Source: AHgI3IYmHUkd07i0lxTtCfg0XcdPPBVIOII7Nh04j8ZwGhVfxn3gjlMk0bR5pxtD+DV6lVi36hn8Pg== X-Received: by 2002:a62:8e19:: with SMTP id k25mr27623449pfe.185.1549718124301; Sat, 09 Feb 2019 05:15:24 -0800 (PST) Received: from localhost.localdomain ([115.97.184.151]) by smtp.gmail.com with ESMTPSA id z8sm6267013pgg.62.2019.02.09.05.15.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 09 Feb 2019 05:15:23 -0800 (PST) From: Jagan Teki To: Maxime Ripard Date: Sat, 9 Feb 2019 18:44:57 +0530 Message-Id: <20190209131500.29954-8-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190209131500.29954-1-jagan@amarulasolutions.com> References: <20190209131500.29954-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stefan Mavrodiev Subject: [U-Boot] [PATCH 07/10] spi: sun4: Add A31 spi controller support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add A31 spi controller support for existing sun4i_spi driver via driver data, this would simply add A31 register along with proper register bits via enum sets. Signed-off-by: Jagan Teki --- drivers/spi/Kconfig | 4 +- drivers/spi/sun4i_spi.c | 84 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 85 insertions(+), 3 deletions(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index ac7fbab841..15207d23c1 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -223,9 +223,9 @@ config STM32_QSPI this ST IP core. config SUN4I_SPI - bool "Allwinner A10 SoCs SPI controller" + bool "Allwinner A10/A31 SoCs SPI controller" help - SPI driver for Allwinner sun4i, sun5i and sun7i SoCs + This enables using the SPI controller on the Allwinner A10/A31 SoCs. config TEGRA114_SPI bool "nVidia Tegra114 SPI driver" diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c index aeed68764c..36f2215f7d 100644 --- a/drivers/spi/sun4i_spi.c +++ b/drivers/spi/sun4i_spi.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -84,6 +85,18 @@ #define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f #define SUN4I_FIFO_STA_TF_CNT_BITS 16 +/* sun6i spi registers */ +#define SUN6I_GBL_CTL_REG 0x04 +#define SUN6I_TFR_CTL_REG 0x08 +#define SUN6I_FIFO_CTL_REG 0x18 +#define SUN6I_FIFO_STA_REG 0x1c +#define SUN6I_CLK_CTL_REG 0x24 +#define SUN6I_BURST_CNT_REG 0x30 +#define SUN6I_XMIT_CNT_REG 0x34 +#define SUN6I_BURST_CTL_REG 0x38 +#define SUN6I_TXDATA_REG 0x200 +#define SUN6I_RXDATA_REG 0x300 + #define SUN4I_SPI_MAX_RATE 24000000 #define SUN4I_SPI_MIN_RATE 3000 #define SUN4I_SPI_DEFAULT_RATE 1000000 @@ -106,6 +119,7 @@ enum sun4i_spi_regs { /* sun spi register bits */ enum sun4i_spi_bits { SPI_GCR_TP, + SPI_GCR_SRST, SPI_TCR_CPHA, SPI_TCR_CPOL, SPI_TCR_CS_ACTIVE_LOW, @@ -133,6 +147,7 @@ struct sun4i_spi_platdata { struct sun4i_spi_priv { struct sun4i_spi_variant *variant; struct clk clk_ahb, clk_mod; + struct reset_ctl reset; u32 base_addr; u32 freq; u32 mode; @@ -255,7 +270,10 @@ static int sun4i_spi_parse_pins(struct udevice *dev) if (pin < 0) break; - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0); + if (IS_ENABLED(CONFIG_MACH_SUN50I)) + sunxi_gpio_set_cfgpin(pin, SUN50I_GPC_SPI0); + else + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0); sunxi_gpio_set_drv(pin, drive); sunxi_gpio_set_pull(pin, pull); } @@ -271,6 +289,8 @@ static inline int sun4i_spi_set_clock(struct udevice *dev, bool enable) if (!enable) { clk_disable(&priv->clk_ahb); clk_disable(&priv->clk_mod); + if (reset_valid(&priv->reset)) + reset_assert(&priv->reset); return 0; } @@ -286,8 +306,18 @@ static inline int sun4i_spi_set_clock(struct udevice *dev, bool enable) goto err_ahb; } + if (reset_valid(&priv->reset)) { + ret = reset_deassert(&priv->reset); + if (ret) { + dev_err(dev, "failed to deassert reset\n"); + goto err_mod; + } + } + return 0; +err_mod: + clk_disable(&priv->clk_mod); err_ahb: clk_disable(&priv->clk_ahb); return ret; @@ -328,6 +358,12 @@ static int sun4i_spi_probe(struct udevice *bus) return ret; } + ret = reset_get_by_index(bus, 0, &priv->reset); + if (ret && ret != -ENOENT) { + dev_err(dev, "failed to get reset\n"); + return ret; + } + sun4i_spi_parse_pins(bus); priv->variant = plat->variant; @@ -351,6 +387,10 @@ static int sun4i_spi_claim_bus(struct udevice *dev) SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | variant->bits[SPI_GCR_TP]); + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + setbits_le32(priv->base_addr + variant->regs[SPI_GCR], + variant->bits[SPI_GCR_SRST]); + setbits_le32(priv->base_addr + variant->regs[SPI_TCR], variant->bits[SPI_TCR_CS_MANUAL] | variant->bits[SPI_TCR_CS_ACTIVE_LOW]); @@ -409,6 +449,9 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen, priv->base_addr + variant->regs[SPI_BC]); writel(SUN4I_XMIT_CNT(nbytes), priv->base_addr + variant->regs[SPI_TC]); + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + writel(SUN4I_BURST_CNT(nbytes), + priv->base_addr + variant->regs[SPI_BCTL]); /* Fill the TX FIFO */ sun4i_spi_fill_fifo(priv, nbytes); @@ -547,17 +590,56 @@ static const unsigned long sun4i_spi_bits[] = { [SPI_FSR_RF_CNT_MASK] = GENMASK(6, 0), }; +static const unsigned long sun8i_spi_regs[] = { + [SPI_GCR] = SUN6I_GBL_CTL_REG, + [SPI_TCR] = SUN6I_TFR_CTL_REG, + [SPI_FCR] = SUN6I_FIFO_CTL_REG, + [SPI_FSR] = SUN6I_FIFO_STA_REG, + [SPI_CCR] = SUN6I_CLK_CTL_REG, + [SPI_BC] = SUN6I_BURST_CNT_REG, + [SPI_TC] = SUN6I_XMIT_CNT_REG, + [SPI_BCTL] = SUN6I_BURST_CTL_REG, + [SPI_TXD] = SUN6I_TXDATA_REG, + [SPI_RXD] = SUN6I_RXDATA_REG, +}; + +static const unsigned long sun8i_spi_bits[] = { + [SPI_GCR_TP] = BIT(7), + [SPI_GCR_SRST] = BIT(31), + [SPI_TCR_CPHA] = BIT(0), + [SPI_TCR_CPOL] = BIT(1), + [SPI_TCR_CS_ACTIVE_LOW] = BIT(2), + [SPI_TCR_CS_SEL] = 4, + [SPI_TCR_CS_MASK] = 0x30, + [SPI_TCR_CS_MANUAL] = BIT(6), + [SPI_TCR_CS_LEVEL] = BIT(7), + [SPI_TCR_XCH] = BIT(31), + [SPI_FCR_RF_RST] = BIT(15), + [SPI_FCR_TF_RST] = BIT(31), + [SPI_FSR_RF_CNT_MASK] = GENMASK(7, 0), +}; + static const struct sun4i_spi_variant sun4i_a10_spi_variant = { .regs = sun4i_spi_regs, .bits = sun4i_spi_bits, .fifo_depth = 64, }; +static const struct sun4i_spi_variant sun8i_h3_spi_variant = { + .regs = sun8i_spi_regs, + .bits = sun8i_spi_bits, + .fifo_depth = 64, +}; + static const struct udevice_id sun4i_spi_ids[] = { { .compatible = "allwinner,sun4i-a10-spi", .data = (ulong)&sun4i_a10_spi_variant, }, + { + .compatible = "allwinner,sun8i-h3-spi", + .data = (ulong)&sun8i_h3_spi_variant, + }, { } };