From patchwork Sat Feb 9 13:14:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1039185 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="MK3qJK9L"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43xXgW4KJgz9sMl for ; Sun, 10 Feb 2019 00:18:47 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 40194C21F69; Sat, 9 Feb 2019 13:17:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 173C2C22007; Sat, 9 Feb 2019 13:15:52 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A7483C21FD9; Sat, 9 Feb 2019 13:15:27 +0000 (UTC) Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) by lists.denx.de (Postfix) with ESMTPS id 9C218C21F3A for ; Sat, 9 Feb 2019 13:15:23 +0000 (UTC) Received: by mail-pl1-f195.google.com with SMTP id e5so3029238plb.5 for ; Sat, 09 Feb 2019 05:15:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HiqGIrl4QDH7j7WoTY/+/9DDysYgsMtZpoNtJ+SlFbo=; b=MK3qJK9L5OoKCgm0a6jVYQrjKfURWd5oOnuUI4Q+cmLiBGQSGwFDaDUuoAaXCTFRUR xleeko3yirXE0YqEVQx/i/5rfzq74tB5obfyl6sb/G4uafnGvO4hXA91l/U9r9fXHezt ZdlBHwWI4LRW20GSPDkLXDU8xlCI2DY1r1f/U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HiqGIrl4QDH7j7WoTY/+/9DDysYgsMtZpoNtJ+SlFbo=; b=KJ4u8jx8hxWMOnIW3lFblBaUIIAlRMePDnDxgyTDqIzcggwITLnYLySF8ZabDnEP35 IaAVFxRe3D1CXv2+m4DQQn0Yte4JTydmf28t+JszAdFZt802h39KyusXkdnFNLV8VCWF 2WgdoBI87OwjDUjh2aFCukyU5Jn74ufWLCYW0r52efmMYsZZX3iLG554bDOtoKomMMi8 1uf9ynejequcxx38TB+eMA7XsResFwkOmPZ0ALqwlTMPSO3Ec2sNPrUavNXL51cEwuBH rPlDNSl8B5fZuXuBKjMfJWKB4FAS5wwF1YItIyasOkeQrdWLtks4yO4tIQx3ENF9WnOd X6Qg== X-Gm-Message-State: AHQUAuZRVL4Rv5YxnpamF92YMzdu35K7GeVuY67qMPZytBZav6q+AQX7 9umvB1w7oJ2n1S8+X80wvKD3fg== X-Google-Smtp-Source: AHgI3IZinvlkLX/9YlLcfyMnprMQKS063IU0Y/OSWsQNbVw1kACnXoNXDj4JPB6ng2wUE6AiHJGmPg== X-Received: by 2002:a17:902:1e9:: with SMTP id b96mr28484434plb.150.1549718122202; Sat, 09 Feb 2019 05:15:22 -0800 (PST) Received: from localhost.localdomain ([115.97.184.151]) by smtp.gmail.com with ESMTPSA id z8sm6267013pgg.62.2019.02.09.05.15.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 09 Feb 2019 05:15:21 -0800 (PST) From: Jagan Teki To: Maxime Ripard Date: Sat, 9 Feb 2019 18:44:56 +0530 Message-Id: <20190209131500.29954-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190209131500.29954-1-jagan@amarulasolutions.com> References: <20190209131500.29954-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stefan Mavrodiev Subject: [U-Boot] [PATCH 06/10] spi: sun4i: Add CLK support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add CLK support to enable AHB and MOD SPI clocks on sun4i_spi driver. Note, that the code will enable and disable clock in claim and release calls to make proper clock and reset handling between claiming and releasing SPI bus. Signed-off-by: Jagan Teki --- drivers/spi/sun4i_spi.c | 56 +++++++++++++++++++++++++++++++++++------ 1 file changed, 48 insertions(+), 8 deletions(-) diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c index d3cf25db6f..aeed68764c 100644 --- a/drivers/spi/sun4i_spi.c +++ b/drivers/spi/sun4i_spi.c @@ -19,6 +19,7 @@ */ #include +#include #include #include #include @@ -29,8 +30,6 @@ #include #include -#include - #include #define SUN4I_RXDATA_REG 0x00 @@ -133,6 +132,7 @@ struct sun4i_spi_platdata { struct sun4i_spi_priv { struct sun4i_spi_variant *variant; + struct clk clk_ahb, clk_mod; u32 base_addr; u32 freq; u32 mode; @@ -263,13 +263,34 @@ static int sun4i_spi_parse_pins(struct udevice *dev) return 0; } -static inline void sun4i_spi_enable_clock(void) +static inline int sun4i_spi_set_clock(struct udevice *dev, bool enable) { - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *const)SUNXI_CCM_BASE; + struct sun4i_spi_priv *priv = dev_get_priv(dev); + int ret; + + if (!enable) { + clk_disable(&priv->clk_ahb); + clk_disable(&priv->clk_mod); + return 0; + } - setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_SPI0)); - writel((1 << 31), &ccm->spi0_clk_cfg); + ret = clk_enable(&priv->clk_ahb); + if (ret) { + dev_err(dev, "failed to enable ahb clock (ret=%d)\n", ret); + return ret; + } + + ret = clk_enable(&priv->clk_mod); + if (ret) { + dev_err(dev, "failed to enable mod clock (ret=%d)\n", ret); + goto err_ahb; + } + + return 0; + +err_ahb: + clk_disable(&priv->clk_ahb); + return ret; } static int sun4i_spi_ofdata_to_platdata(struct udevice *bus) @@ -293,8 +314,20 @@ static int sun4i_spi_probe(struct udevice *bus) { struct sun4i_spi_platdata *plat = dev_get_platdata(bus); struct sun4i_spi_priv *priv = dev_get_priv(bus); + int ret; + + ret = clk_get_by_name(bus, "ahb", &priv->clk_ahb); + if (ret) { + dev_err(dev, "failed to get ahb clock\n"); + return ret; + } + + ret = clk_get_by_name(bus, "mod", &priv->clk_mod); + if (ret) { + dev_err(dev, "failed to get mod clock\n"); + return ret; + } - sun4i_spi_enable_clock(); sun4i_spi_parse_pins(bus); priv->variant = plat->variant; @@ -308,6 +341,11 @@ static int sun4i_spi_claim_bus(struct udevice *dev) { struct sun4i_spi_priv *priv = dev_get_priv(dev->parent); struct sun4i_spi_variant *variant = priv->variant; + int ret; + + ret = sun4i_spi_set_clock(dev->parent, true); + if (ret) + return ret; setbits_le32(priv->base_addr + variant->regs[SPI_GCR], SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | @@ -328,6 +366,8 @@ static int sun4i_spi_release_bus(struct udevice *dev) clrbits_le32(priv->base_addr + variant->regs[SPI_GCR], SUN4I_CTL_ENABLE); + sun4i_spi_set_clock(dev->parent, false); + return 0; }