[GIT,PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v5.1

Message ID cover.1549623801.git.horms+renesas@verge.net.au
State New
Headers show
Series
  • [GIT,PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v5.1
Related show

Pull-request

https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-arm64-dt2-for-v5.1

Message

Simon Horman Feb. 8, 2019, 11:13 a.m.
Hi Olof, Hi Kevin, Hi Arnd,

Please consider these second round of Renesas ARM64 based SoC DT updates for v5.1.

This pull request is based on the previous round of
such requests, tagged as renesas-arm64-dt-for-v5.1,
which you have already pulled.


The following changes since commit 3e279a1d44d73aea9ce428ae68e76bf85117031a:

  arm64: dts: renesas: r8a77990: ebisu: Enable HS400 of SDHI3 (2019-01-23 09:45:41 +0100)

are available in the git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-arm64-dt2-for-v5.1

for you to fetch changes up to ee20aeefb53f6ffabed5b1a3b859294197eeb351:

  arm64: dts: renesas: cat875: Enable PCIe support (2019-02-08 11:49:09 +0100)

----------------------------------------------------------------
Second Round of Renesas ARM64 Based SoC DT Updates for v5.1

* R-Car Gen3 SoC based Salvator-X, Salvator-XS and ULCB boards
  - Enable HS400 support for eMMC

* R-Car E3 (r7a77990) SoC
  - Add OPPs table for cpu devices

* RZ/G2E (r8a774c0) SoC
  - Describe TMU, CMT, SDHI devices in DT
  - Describe pincontrol support for SCIF2 device in DT
  - Add OPPs table for cpu devices

* RZ/G2E (r8a774c0) based EK874 board and CAT875 sub-board,
  and CAT874 board
  - Initial support

----------------------------------------------------------------
Biju Das (9):
      arm64: dts: renesas: Add Si-Linux CAT874 board support
      arm64: dts: renesas: Add Si-Linux EK874 board support
      arm64: dts: renesas: r8a774c0-cat874: Add pincontrol support to scif2
      arm64: dts: renesas: r8a774c0-cat874: Add uSD support
      arm64: dts: renesas: cat875: Add ethernet support
      arm64: dts: renesas: r8a774c0: Add CMT device nodes
      arm64: dts: renesas: r8a774c0: Add TMU device nodes
      arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support
      arm64: dts: renesas: cat875: Enable PCIe support

Fabrizio Castro (1):
      arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices

Niklas Söderlund (1):
      arm64: dts: renesas: enable HS400 on R-Car Gen3

Takeshi Kihara (1):
      arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices

 arch/arm64/boot/dts/renesas/Makefile             |   1 +
 arch/arm64/boot/dts/renesas/cat875.dtsi          |  44 +++++++
 arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts  | 106 +++++++++++++++
 arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts   |  14 ++
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi        | 160 +++++++++++++++++++++++
 arch/arm64/boot/dts/renesas/r8a77990.dtsi        |  25 ++++
 arch/arm64/boot/dts/renesas/salvator-common.dtsi |   1 +
 arch/arm64/boot/dts/renesas/ulcb.dtsi            |   1 +
 8 files changed, 352 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/cat875.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts

Comments

Sergei Shtylyov Feb. 8, 2019, 12:52 p.m. | #1
Hello!

On 02/08/2019 02:13 PM, Simon Horman wrote:

> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> 
> This patch defines OOP tables for all CPUs, similarly to
> what done by Takeshi Kihara and Yoshihiro Kaneko for the
> R8A77990.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
[...]
> @@ -55,6 +76,8 @@
>  			power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
>  			next-level-cache = <&L2_CA53>;
>  			enable-method = "psci";
> +			clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;

   Need space after =...

> +			operating-points-v2 = <&cluster1_opp>;
>  		};
>  
>  		a53_1: cpu@1 {
> @@ -64,6 +87,8 @@
>  			power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
>  			next-level-cache = <&L2_CA53>;
>  			enable-method = "psci";
> +			clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;


   Here as well...

> +			operating-points-v2 = <&cluster1_opp>;
>  		};
>  
>  		L2_CA53: cache-controller-0 {

MBR, Sergei
Fabrizio Castro Feb. 8, 2019, 3:26 p.m. | #2
Hello Sergei,

Thank you for your feedback!

> -----Original Message-----
> From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Sent: 08 February 2019 12:53
> To: Simon Horman <horms+renesas@verge.net.au>; linux-renesas-soc@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org; Magnus Damm <magnus.damm@gmail.com>; Fabrizio Castro
> <fabrizio.castro@bp.renesas.com>
> Subject: Re: [PATCH 08/12] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices
>
> Hello!
>
> On 02/08/2019 02:13 PM, Simon Horman wrote:
>
> > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >
> > This patch defines OOP tables for all CPUs, similarly to
> > what done by Takeshi Kihara and Yoshihiro Kaneko for the
> > R8A77990.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> [...]
> > @@ -55,6 +76,8 @@
> >  power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
> >  next-level-cache = <&L2_CA53>;
> >  enable-method = "psci";
> > +clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
>
>    Need space after =...

Doh! Simon, do you want me to send another version to fix both spacing issues?

Thanks,
Fab

>
> > +operating-points-v2 = <&cluster1_opp>;
> >  };
> >
> >  a53_1: cpu@1 {
> > @@ -64,6 +87,8 @@
> >  power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
> >  next-level-cache = <&L2_CA53>;
> >  enable-method = "psci";
> > +clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
>
>
>    Here as well...
>
> > +operating-points-v2 = <&cluster1_opp>;
> >  };
> >
> >  L2_CA53: cache-controller-0 {
>
> MBR, Sergei


Renesas Electronics Europe GmbH,Geschaeftsfuehrer/President : Michael Hannawald, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany,Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647
Simon Horman Feb. 11, 2019, 9:49 a.m. | #3
On Fri, Feb 08, 2019 at 03:26:49PM +0000, Fabrizio Castro wrote:
> Hello Sergei,
> 
> Thank you for your feedback!
> 
> > -----Original Message-----
> > From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> > Sent: 08 February 2019 12:53
> > To: Simon Horman <horms+renesas@verge.net.au>; linux-renesas-soc@vger.kernel.org
> > Cc: linux-arm-kernel@lists.infradead.org; Magnus Damm <magnus.damm@gmail.com>; Fabrizio Castro
> > <fabrizio.castro@bp.renesas.com>
> > Subject: Re: [PATCH 08/12] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices
> >
> > Hello!
> >
> > On 02/08/2019 02:13 PM, Simon Horman wrote:
> >
> > > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > >
> > > This patch defines OOP tables for all CPUs, similarly to
> > > what done by Takeshi Kihara and Yoshihiro Kaneko for the
> > > R8A77990.
> > >
> > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > [...]
> > > @@ -55,6 +76,8 @@
> > >  power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
> > >  next-level-cache = <&L2_CA53>;
> > >  enable-method = "psci";
> > > +clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
> >
> >    Need space after =...
> 
> Doh! Simon, do you want me to send another version to fix both spacing issues?

Likewise, sorry I didn't notice that earlier.

I'd rather not re-send this pull request just to resolve whitespace issues.
So please send an incremental patch for now.
Fabrizio Castro Feb. 14, 2019, 12:57 p.m. | #4
Hello Simon,

> From: Simon Horman <horms@verge.net.au>
> Sent: 11 February 2019 09:50
> Subject: Re: [PATCH 08/12] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices
>
> On Fri, Feb 08, 2019 at 03:26:49PM +0000, Fabrizio Castro wrote:
> > Hello Sergei,
> >
> > Thank you for your feedback!
> >
> > > -----Original Message-----
> > > From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> > > Sent: 08 February 2019 12:53
> > > To: Simon Horman <horms+renesas@verge.net.au>; linux-renesas-soc@vger.kernel.org
> > > Cc: linux-arm-kernel@lists.infradead.org; Magnus Damm <magnus.damm@gmail.com>; Fabrizio Castro
> > > <fabrizio.castro@bp.renesas.com>
> > > Subject: Re: [PATCH 08/12] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices
> > >
> > > Hello!
> > >
> > > On 02/08/2019 02:13 PM, Simon Horman wrote:
> > >
> > > > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > >
> > > > This patch defines OOP tables for all CPUs, similarly to
> > > > what done by Takeshi Kihara and Yoshihiro Kaneko for the
> > > > R8A77990.
> > > >
> > > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > > [...]
> > > > @@ -55,6 +76,8 @@
> > > >  power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
> > > >  next-level-cache = <&L2_CA53>;
> > > >  enable-method = "psci";
> > > > +clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
> > >
> > >    Need space after =...
> >
> > Doh! Simon, do you want me to send another version to fix both spacing issues?
>
> Likewise, sorry I didn't notice that earlier.
>
> I'd rather not re-send this pull request just to resolve whitespace issues.
> So please send an incremental patch for now.

Thanks, will do.

Cheers,
Fab


Renesas Electronics Europe GmbH,Geschaeftsfuehrer/President : Michael Hannawald, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany,Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647
Arnd Bergmann Feb. 15, 2019, 2:44 p.m. | #5
On Fri, Feb 8, 2019 at 12:13 PM Simon Horman <horms+renesas@verge.net.au> wrote:

> Second Round of Renesas ARM64 Based SoC DT Updates for v5.1
>
> * R-Car Gen3 SoC based Salvator-X, Salvator-XS and ULCB boards
>   - Enable HS400 support for eMMC
>
> * R-Car E3 (r7a77990) SoC
>   - Add OPPs table for cpu devices
>
> * RZ/G2E (r8a774c0) SoC
>   - Describe TMU, CMT, SDHI devices in DT
>   - Describe pincontrol support for SCIF2 device in DT
>   - Add OPPs table for cpu devices
>
> * RZ/G2E (r8a774c0) based EK874 board and CAT875 sub-board,
>   and CAT874 board
>   - Initial support

Pulled into arm/dt, thanks!

      Arnd