From patchwork Thu Feb 7 12:54:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kejia Hu X-Patchwork-Id: 1038051 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=codethink.co.uk Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43wJRS0XcBz9s4V for ; Fri, 8 Feb 2019 00:04:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726994AbfBGNEB (ORCPT ); Thu, 7 Feb 2019 08:04:01 -0500 Received: from imap1.codethink.co.uk ([176.9.8.82]:33054 "EHLO imap1.codethink.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726949AbfBGNEB (ORCPT ); Thu, 7 Feb 2019 08:04:01 -0500 Received: from [167.98.27.226] (helo=devhw0) by imap1.codethink.co.uk with esmtpsa (Exim 4.84_2 #1 (Debian)) id 1grjLS-0008Ln-HP; Thu, 07 Feb 2019 13:03:58 +0000 Received: from terry by devhw0 with local (Exim 4.89) (envelope-from ) id 1grjBx-0002IT-RP; Thu, 07 Feb 2019 12:54:09 +0000 From: Kejia Hu To: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Ben Dooks , Thomas Preston Subject: [PATCH 3/5] clk: tegra: add tegra30 automotive init Date: Thu, 7 Feb 2019 12:54:06 +0000 Message-Id: <20190207125408.8776-4-kejia.hu@codethink.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190207125408.8776-1-kejia.hu@codethink.co.uk> References: <20190207125408.8776-1-kejia.hu@codethink.co.uk> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Ben Dooks Add intialisation for the tegra30 automotive parts which have different initialisation requirements than the tegra30. These have been copied from the 2.6 BSP supplied by nvidia for these parts. Signed-off-by: Ben Dooks Signed-off-by: Thomas Preston --- drivers/clk/tegra/clk-tegra30.c | 83 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 82 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index fa8d573ac626..c483bdb562f6 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -22,6 +22,7 @@ #include #include +#include #include #include @@ -1278,9 +1279,89 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, }; +/* Tegra30 automotive part initialisation table. + * + * These values have been derived from the Nvidia supplied BSP for their + * automotive parts. + */ +static struct tegra_clk_init_table init_table_t30a[] __initdata = { + { TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 1 }, + { TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 1 }, + { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 }, + { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 1 }, + { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 }, + { TEGRA30_CLK_PLL_P_OUT1, TEGRA30_CLK_CLK_MAX, 9600000, 1 }, + { TEGRA30_CLK_PLL_P_OUT2, TEGRA30_CLK_CLK_MAX, 48000000, 1 }, + { TEGRA30_CLK_PLL_P_OUT3, TEGRA30_CLK_CLK_MAX, 102000000, 1 }, + { TEGRA30_CLK_PLL_P_OUT4, TEGRA30_CLK_CLK_MAX, 102000000, 1 }, + { TEGRA30_CLK_FUSE, TEGRA30_CLK_CLK_MAX, 12000000, 1 }, + { TEGRA30_CLK_KFUSE, TEGRA30_CLK_CLK_MAX, 12000000, 1 }, + { TEGRA30_CLK_CCLK_G, TEGRA30_CLK_CLK_MAX, 900000000, 0 }, + { TEGRA30_CLK_CCLK_LP,TEGRA30_CLK_CLK_MAX, 484000000, 0 }, + { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 552960000, 1 }, + { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 24576000, 1 }, + { TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 24576000, 1 }, + { TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_CLK_M, 0, 0 }, + { TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1 }, + { TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1 }, + { TEGRA30_CLK_I2S0, TEGRA30_CLK_CLK_M, 12288000, 0 }, + { TEGRA30_CLK_I2S1, TEGRA30_CLK_CLK_M, 12288000, 0 }, + { TEGRA30_CLK_I2S2, TEGRA30_CLK_CLK_M, 12288000, 0 }, + { TEGRA30_CLK_I2S3, TEGRA30_CLK_CLK_M, 12288000, 0 }, + { TEGRA30_CLK_I2S4, TEGRA30_CLK_CLK_M, 12288000, 0 }, + { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 108000000, 0 }, + { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 }, + { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 }, + { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 104000000, 0 }, + { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 }, + { TEGRA30_CLK_SDMMC4, TEGRA30_CLK_PLL_P, 48000000, 0 }, + { TEGRA30_CLK_NOR, TEGRA30_CLK_PLL_P, 102000000, 0 }, + { TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1 }, + { TEGRA30_CLK_PLL_M_OUT1, TEGRA30_CLK_CLK_MAX, 312500000, 1 }, + { TEGRA30_CLK_SCLK, TEGRA30_CLK_PLL_M_OUT1, 312500000, 1 }, + { TEGRA30_CLK_HCLK, TEGRA30_CLK_CLK_MAX, 312500000, 1 }, + { TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 312500000/2, 1 }, + { TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 }, + { TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1 }, + { TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1 }, + { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 484000000, 1 }, + /* initialse PLL_D and set it up before the display code for test */ + { TEGRA30_CLK_PLL_D, TEGRA30_CLK_CLK_MAX, 257800000, 1 }, + /* set EPP clock to TEGRA30_CLK_PLL_C */ + { TEGRA30_CLK_EPP, TEGRA30_CLK_PLL_C, 484000000, 0 }, + { TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_M, 15822784, 1 }, + { TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_M, 100000000, 1 }, + { TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_M, 100000000, 1 }, + { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_M, 100000000, 1 }, + { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_M, 100000000, 1 }, + { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_M, 100000000, 1 }, + { TEGRA30_CLK_SE, TEGRA30_CLK_PLL_M, 625000000, 1 }, + { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 242000000, 0 }, + { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 275000000, 0 }, + { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 275000000, 0 }, + { TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 }, + { TEGRA30_CLK_GR2D, TEGRA30_CLK_CLK_MAX, 484000000, 0 }, + { TEGRA30_CLK_GR3D, TEGRA30_CLK_CLK_MAX, 484000000, 0 }, + { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 484000000, 0 }, + { TEGRA30_CLK_D_AUDIO, TEGRA30_CLK_PLL_A_OUT0, 24576000, 0 }, + { TEGRA30_CLK_MPE, TEGRA30_CLK_PLL_C, 484000000, 0 }, + { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 484000000, 0 }, + { TEGRA30_CLK_VI, TEGRA30_CLK_PLL_P, 470000000, 0 }, + { TEGRA30_CLK_VI_SENSOR, TEGRA30_CLK_PLL_P, 150000000, 0 }, + { TEGRA30_CLK_PWM, TEGRA30_CLK_CLK_32K, 32768, 0 }, + { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, /* This MUST be the last entry. */ +}; + static void __init tegra30_clock_apply_init_table(void) { - tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX); + struct tegra_clk_init_table *table = init_table; + + if (soc_is_tegra_auto()) { + pr_info("Initialise Tegra Automotive clocks\n"); + table = init_table_t30a; + } + + tegra_init_from_table(table, clks, TEGRA30_CLK_CLK_MAX); } /*