From patchwork Thu Jul 7 23:44:05 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Scott Wood X-Patchwork-Id: 103747 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 36A23B6F18 for ; Fri, 8 Jul 2011 09:56:15 +1000 (EST) Received: from localhost ([::1]:45739 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QeyQU-00082y-U3 for incoming@patchwork.ozlabs.org; Thu, 07 Jul 2011 19:56:11 -0400 Received: from eggs.gnu.org ([140.186.70.92]:48969) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QeyF3-00064L-TS for qemu-devel@nongnu.org; Thu, 07 Jul 2011 19:44:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QeyF2-000804-Be for qemu-devel@nongnu.org; Thu, 07 Jul 2011 19:44:21 -0400 Received: from va3ehsobe003.messaging.microsoft.com ([216.32.180.13]:10801 helo=VA3EHSOBE003.bigfish.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QeyF1-0007zf-Ts for qemu-devel@nongnu.org; Thu, 07 Jul 2011 19:44:20 -0400 Received: from mail151-va3-R.bigfish.com (10.7.14.245) by VA3EHSOBE003.bigfish.com (10.7.40.23) with Microsoft SMTP Server id 14.1.225.22; Thu, 7 Jul 2011 23:44:18 +0000 Received: from mail151-va3 (localhost.localdomain [127.0.0.1]) by mail151-va3-R.bigfish.com (Postfix) with ESMTP id ECCE5174848F; Thu, 7 Jul 2011 23:44:18 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839h944h61h) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail151-va3 (localhost.localdomain [127.0.0.1]) by mail151-va3 (MessageSwitch) id 1310082258739489_31241; Thu, 7 Jul 2011 23:44:18 +0000 (UTC) Received: from VA3EHSMHS009.bigfish.com (unknown [10.7.14.254]) by mail151-va3.bigfish.com (Postfix) with ESMTP id 7633592004D; Thu, 7 Jul 2011 23:44:18 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS009.bigfish.com (10.7.99.19) with Microsoft SMTP Server (TLS) id 14.1.225.22; Thu, 7 Jul 2011 23:44:07 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.289.8; Thu, 7 Jul 2011 18:44:06 -0500 Received: from schlenkerla.am.freescale.net (schlenkerla.am.freescale.net [10.82.121.12]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p67Ni5Wh024933; Thu, 7 Jul 2011 18:44:06 -0500 (CDT) Date: Thu, 7 Jul 2011 18:44:05 -0500 From: Scott Wood To: Message-ID: <20110707234405.GC6748@schlenkerla.am.freescale.net> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20110707234337.GA6720@schlenkerla.am.freescale.net> User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginatorOrg: freescale.com X-detected-operating-system: by eggs.gnu.org: Windows 2000 SP2+, XP SP1+ (seldom 98) X-Received-From: 216.32.180.13 Cc: qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH 3/4] ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pages X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This definition is backward compatible with MAV=1.0 as long as the guest does not set reserved bits in MAS1/MAS4. Also, fix the shift in booke206_tlb_to_page_size -- it's the base that should be able to hold a 4G page size, not the shift count. Signed-off-by: Scott Wood --- Unchanged in patchset v2 hw/ppce500_mpc8544ds.c | 2 +- target-ppc/cpu.h | 4 ++-- target-ppc/helper.c | 5 +++-- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c index 3626e26..1aed612 100644 --- a/hw/ppce500_mpc8544ds.c +++ b/hw/ppce500_mpc8544ds.c @@ -187,7 +187,7 @@ out: /* Create -kernel TLB entries for BookE, linearly spanning 256MB. */ static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size) { - return (ffs(size >> 10) - 1) >> 1; + return ffs(size >> 10) - 1; } static void mmubooke_create_initial_mapping(CPUState *env, diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index f8bf2b1..9cf8327 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -654,8 +654,8 @@ enum { #define MAS0_ATSEL_TLB 0 #define MAS0_ATSEL_LRAT MAS0_ATSEL -#define MAS1_TSIZE_SHIFT 8 -#define MAS1_TSIZE_MASK (0xf << MAS1_TSIZE_SHIFT) +#define MAS1_TSIZE_SHIFT 7 +#define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT) #define MAS1_TS_SHIFT 12 #define MAS1_TS (1 << MAS1_TS_SHIFT) diff --git a/target-ppc/helper.c b/target-ppc/helper.c index 176128a..892c6e3 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -1293,7 +1293,7 @@ target_phys_addr_t booke206_tlb_to_page_size(CPUState *env, ppcmas_tlb_t *tlb) { uint32_t tlbncfg; int tlbn = booke206_tlbm_to_tlbn(env, tlb); - target_phys_addr_t tlbm_size; + int tlbm_size; tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; @@ -1301,9 +1301,10 @@ target_phys_addr_t booke206_tlb_to_page_size(CPUState *env, ppcmas_tlb_t *tlb) tlbm_size = (tlb->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; } else { tlbm_size = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT; + tlbm_size <<= 1; } - return (1 << (tlbm_size << 1)) << 10; + return 1024ULL << tlbm_size; } /* TLB check function for MAS based SoftTLBs */