From patchwork Tue Feb 5 05:59:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Raghavendra, Vignesh" X-Patchwork-Id: 1036450 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="KzId+q+X"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43tvJq1sgbz9sMp for ; Tue, 5 Feb 2019 17:08:27 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E94F8C21F75; Tue, 5 Feb 2019 06:05:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7E26DC21F47; Tue, 5 Feb 2019 06:02:27 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4F3B1C21E6C; Tue, 5 Feb 2019 06:00:35 +0000 (UTC) Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lists.denx.de (Postfix) with ESMTPS id 01E3EC21F16 for ; Tue, 5 Feb 2019 06:00:29 +0000 (UTC) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x1560KqA009024; Tue, 5 Feb 2019 00:00:20 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1549346420; bh=pyBhBzUKUMVlQi1gYQFUYdMPhq17v/QBzelN2XkS8Os=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=KzId+q+Xee6l85VcoNh2NCvCsXKrgEazQ8mzCIrt5iOjrEoIyMv8JLtaoN/ME+5x2 TT1LDxMNxE8eniOhLZNK3M2LJzb7asLYGmY62R0mc+c7p0E65bVMrMpFomx2CgkPb3 RMqOY+TLs8kKHzlW+XjxSLR/jxmWj3uvPPyUSCTM= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x1560KmD014710 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 5 Feb 2019 00:00:20 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Tue, 5 Feb 2019 00:00:19 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Tue, 5 Feb 2019 00:00:19 -0600 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x155wVWL006226; Tue, 5 Feb 2019 00:00:14 -0600 From: Vignesh R To: Jagan Teki Date: Tue, 5 Feb 2019 11:29:27 +0530 Message-ID: <20190205055929.24168-19-vigneshr@ti.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205055929.24168-1-vigneshr@ti.com> References: <20190205055929.24168-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Marek Vasut , Tom Rini , Stefan Roese , Nobuhiro Iwamatsu , Boris Brezillon , Michal Simek , u-boot@lists.denx.de, Rajat Srivastava , Miquel Raynal Subject: [U-Boot] [PATCH v4 18/20] configs: Remove SF_DUAL_FLASH X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" SF_DUAL_FLASH claims to enable support for SF_DUAL_STACKED_FLASH and SF_DUAL_PARALLEL_FLASH. But, in current U-Boot code, grepping for above enums yield no user and therefore support seems to be incomplete. Remove these configs so as to avoid confusion. Signed-off-by: Vignesh R Reviewed-by: Jagan Teki Tested-by: Jagan Teki #zynq-microzed --- configs/topic_miamilite_defconfig | 1 - configs/topic_miamiplus_defconfig | 1 - configs/xilinx_zynqmp_mini_qspi_defconfig | 1 - configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revB_defconfig | 1 - .../xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - .../xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 - configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 - doc/SPI/README.dual-flash | 92 ------------------- include/configs/socfpga_stratix10_socdk.h | 1 - 17 files changed, 108 deletions(-) delete mode 100644 doc/SPI/README.dual-flash diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index e4d52f6a915e..95fa7678d639 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -40,7 +40,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_DEBUG_UART_ZYNQ=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index f742838d7c1f..6d753c0326a1 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -39,7 +39,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set # CONFIG_NETDEVICES is not set diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index 3ec435e7ffe7..911d1beed2e1 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -54,7 +54,6 @@ CONFIG_SPL_DM_SEQ_ALIAS=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig index 9026f00649bb..1b0df0c7b9a3 100644 --- a/configs/xilinx_zynqmp_zc1232_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig @@ -38,7 +38,6 @@ CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig index 3eed06976053..043ce80b5916 100644 --- a/configs/xilinx_zynqmp_zc1254_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig @@ -38,7 +38,6 @@ CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zc1275_revA_defconfig b/configs/xilinx_zynqmp_zc1275_revA_defconfig index 8bd7c9c57842..51ed37038d40 100644 --- a/configs/xilinx_zynqmp_zc1275_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revA_defconfig @@ -38,7 +38,6 @@ CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zc1275_revB_defconfig b/configs/xilinx_zynqmp_zc1275_revB_defconfig index 9f023c2bd2bd..04c73b7d0170 100644 --- a/configs/xilinx_zynqmp_zc1275_revB_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revB_defconfig @@ -42,7 +42,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index f2caac790a1a..dd6f50df4ee4 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -62,7 +62,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig index 10e0fca65578..e742406cb22d 100644 --- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig @@ -48,7 +48,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index 30d3147a7a8b..d61ca4d37e45 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -75,7 +75,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index bada5e117317..e4d656889287 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -73,7 +73,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 3c4ac01b220c..ded0c6f0edcd 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -73,7 +73,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig index 90fd431df3dd..3025ace26116 100644 --- a/configs/xilinx_zynqmp_zcu104_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig @@ -58,7 +58,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig index eb30e2398f2c..d1d39e2bc63b 100644 --- a/configs/xilinx_zynqmp_zcu104_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig @@ -59,7 +59,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_zcu106_revA_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig index 9e8eb5f483a2..13f2e9da4d29 100644 --- a/configs/xilinx_zynqmp_zcu106_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu106_revA_defconfig @@ -69,7 +69,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/doc/SPI/README.dual-flash b/doc/SPI/README.dual-flash deleted file mode 100644 index 6c88d65dd49f..000000000000 --- a/doc/SPI/README.dual-flash +++ /dev/null @@ -1,92 +0,0 @@ -SPI/QSPI Dual flash connection modes: -===================================== - -This describes how SPI/QSPI flash memories are connected to a given -controller in a single chip select line. - -Current spi_flash framework supports, single flash memory connected -to a given controller with single chip select line, but there are some -hw logics(ex: xilinx zynq qspi) that describes two/dual memories are -connected with a single chip select line from a controller. - -"dual_flash" from include/spi.h describes these types of connection mode - -Possible connections: --------------------- -SF_SINGLE_FLASH: - - single spi flash memory connected with single chip select line. - - +------------+ CS +---------------+ - | |----------------------->| | - | Controller | I0[3:0] | Flash memory | - | SPI/QSPI |<======================>| (SPI/QSPI) | - | | CLK | | - | |----------------------->| | - +------------+ +---------------+ - -SF_DUAL_STACKED_FLASH: - - dual spi/qspi flash memories are connected with a single chipselect - line and these two memories are operating stacked fasion with shared buses. - - xilinx zynq qspi controller has implemented this feature [1] - - +------------+ CS +---------------+ - | |---------------------->| | - | | I0[3:0] | Upper Flash | - | | +=========>| memory | - | | | CLK | (SPI/QSPI) | - | | | +---->| | - | Controller | CS | | +---------------+ - | SPI/QSPI |------------|----|---->| | - | | I0[3:0] | | | Lower Flash | - | |<===========+====|====>| memory | - | | CLK | | (SPI/QSPI) | - | |-----------------+---->| | - +------------+ +---------------+ - - - two memory flash devices should has same hw part attributes (like size, - vendor..etc) - - Configurations: - on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG - Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory - Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory - - Operation: - accessing memories serially like one after another. - by default, if U_PAGE is unset lower memory should accessible, - once user wants to access upper memory need to set U_PAGE. - -SPI_FLASH_CONN_DUALPARALLEL: - - dual spi/qspi flash memories are connected with a single chipselect - line and these two memories are operating parallel with separate buses. - - xilinx zynq qspi controller has implemented this feature [1] - - +-------------+ CS +---------------+ - | |---------------------->| | - | | I0[3:0] | Upper Flash | - | |<=====================>| memory | - | | CLK | (SPI/QSPI) | - | |---------------------->| | - | Controller | CS +---------------+ - | SPI/QSPI |---------------------->| | - | | I0[3:0] | Lower Flash | - | |<=====================>| memory | - | | CLK | (SPI/QSPI) | - | |---------------------->| | - +-------------+ +---------------+ - - - two memory flash devices should has same hw part attributes (like size, - vendor..etc) - - Configurations: - Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG register. - - Operation: - Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the lower memory - and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in the upper memory. - -Note: Technically there is only one CS line from the controller, but -zynq qspi controller has an internal hw logic to enable additional CS -when controller is configured for dual memories. - -[1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf - --- -Jagannadha Sutradharudu Teki -05-01-2014. diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h index f9319a2234ff..0e73239f568c 100644 --- a/include/configs/socfpga_stratix10_socdk.h +++ b/include/configs/socfpga_stratix10_socdk.h @@ -57,7 +57,6 @@ */ #ifdef CONFIG_CADENCE_QSPI /* Enable it if you want to use dual-stacked mode */ -#undef CONFIG_SF_DUAL_FLASH /*#define CONFIG_QSPI_RBF_ADDR 0x720000*/ /* Flash device info */