From patchwork Fri Feb 1 16:16:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1034888 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="UbNTxnwG"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43rj182kSYz9sN9 for ; Sat, 2 Feb 2019 03:17:16 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730780AbfBAQRN (ORCPT ); Fri, 1 Feb 2019 11:17:13 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:15189 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730779AbfBAQRN (ORCPT ); Fri, 1 Feb 2019 11:17:13 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 01 Feb 2019 08:17:14 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 01 Feb 2019 08:17:12 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 01 Feb 2019 08:17:12 -0800 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 1 Feb 2019 16:17:11 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Fri, 1 Feb 2019 16:17:11 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 01 Feb 2019 08:17:11 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter , Daniel Lezcano , Thomas Gleixner CC: , , Joseph Lo Subject: [PATCH V6 5/7] arm64: dts: tegra210: add CPU idle states properties Date: Sat, 2 Feb 2019 00:16:52 +0800 Message-ID: <20190201161654.18315-6-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190201161654.18315-1-josephl@nvidia.com> References: <20190201161654.18315-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1549037834; bh=flTY705hJAZY/7hKXgSgMMFWBb1O9aTKyqClGqqGHYY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=UbNTxnwGXTZA5J3y+fvaqE9F3cRib+69qRbCgHhR+/8LU9MULx/JHWNkR+1JV+FRp u7xdpcLlZTqoy9FaqCg1fKtxTvApLMnHL3rUDvKX+gwUESFBTxfuAq6DLjo1CdcqnC 59xc37NQ18BuHWlKbQM7W9qlrKfk8thd2prIxiDQUi36QLtLZ3ZtbKpzLKFoncAfL9 a85VTfxMKX97IHALDplLXkKrSaNHozola3Jz6+5wh51GAJJgFjTpKkdmn2p+btshfS em1jivzzE6GM0GO3WEurNOxIAfbt23PNSGgzJgdFGJijw04d2SJEEpoLHK9+f8YaXO +zOA+hisTaN9w== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add idle states properties for generic ARM CPU idle driver. This includes a C7 state which is the power down state of CPU cores. Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- v6: * add ack tag from Jon. v5: * no change v4: * no change v3: * no change v2: * add entry-latency-us and exit-latency-us properties Note: This dt patch depends on the DT changes in below series. http://patchwork.ozlabs.org/project/linux-tegra/list/?series=84380 --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 2b387364afc3..75534692604c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1318,24 +1318,43 @@ <&dfll>; clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; clock-latency = <300000>; + cpu-idle-states = <&C7>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <1>; + cpu-idle-states = <&C7>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <2>; + cpu-idle-states = <&C7>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <3>; + cpu-idle-states = <&C7>; + }; + + idle-states { + entry-method = "psci"; + + C7: c7 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000007>; + entry-latency-us = <250>; + exit-latency-us = <100>; + min-residency-us = <1000>; + wakeup-latency-us = <130>; + idle-state-name = "c7-cpu-powergated"; + status = "disabled"; + }; }; };