From patchwork Fri Feb 1 13:28:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1034771 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="BJ3zxi41"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43rdH534w0z9sDX for ; Sat, 2 Feb 2019 00:29:05 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728103AbfBAN3F (ORCPT ); Fri, 1 Feb 2019 08:29:05 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:54084 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728081AbfBAN3E (ORCPT ); Fri, 1 Feb 2019 08:29:04 -0500 Received: by mail-wm1-f68.google.com with SMTP id d15so6137248wmb.3 for ; Fri, 01 Feb 2019 05:29:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vG6AIuNphuzMHBFx759aEugmfd4bRy8jdS1AkMTXt/Y=; b=BJ3zxi41Kcl+8iCQmRJBpCMP7RD8SrnZZ7B7/VbkMLQFPyiKu/uK69V+mYGr22VXty I/NUHVFF4lTUlYFawWW+6JD8VVYacDBwzz2m1D+T0C/qAQVvpUxUdZ/Qpf472G0Y3zjo j2uRgT+j0mS5UlbafftySrzOA6nf8N7AqQMgHbg88SgKF7N8feXD8qCCTWOwsBR5yU63 dljwu11jRxtwAGO1T/+nSnZ2jfj8ObqXsGpiEfdUXAf9lxuqIcLHh5xHbxKbmlC7qTCT CT8ZGnmnzjV1jm40TBGJ0NR1sr99TrZbHbGS9ZrBfkKJWHA6cDUwIQBcucLF3BRAwG09 JBZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vG6AIuNphuzMHBFx759aEugmfd4bRy8jdS1AkMTXt/Y=; b=VKGpMIbk5QjebJFTAoOG2t3tnfU5UgRumg0s8xwIv3083/ghHLRSpqAt9KZr7wJNq8 /fpaBR61z7qHMC14YMHD57LSOIy9D7we44r4I+CTW0QuynRza6jBiXZ3rSLLql5rLmXU Ltd364bKB39GfZ61M1mYWLyu5E3A1JpSPGL7gO6PsABn6KgObeUf8SIyunndg7b8sMw6 C86TR/TF8CWX+/qtT1kSR1fL/0X6zwHAJOFkx53fcBlvrOR/HJOMEgeHgiyga6piV9d4 JDIlk/s7WTCccnM7QqdVk4vtFeSzPvYmV83o2hP8egWk4kqB+R3mBtYGZU2KlbLwEtqZ lEuA== X-Gm-Message-State: AHQUAubtKo5AhxZ9F2FrbhUy70+wc0N9YgHkiDMtYRZ6Z1zarpaeeBZh AcL44Cbvgqa7XY8/MGHdUMg= X-Google-Smtp-Source: AHgI3IZvR1BALPGNkurBoMmVsxhE32GbnBS9qNdIQUrKM0cZr23zJbl12hk8zVwh3KGFKVRNR2KYGA== X-Received: by 2002:a1c:9692:: with SMTP id y140mr2552967wmd.67.1549027742237; Fri, 01 Feb 2019 05:29:02 -0800 (PST) Received: from localhost (pD9E51040.dip0.t-ipconnect.de. [217.229.16.64]) by smtp.gmail.com with ESMTPSA id d4sm11639307wrp.89.2019.02.01.05.29.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 01 Feb 2019 05:29:01 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Mikko Perttunen , Dmitry Osipenko , dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH v3 15/16] drm/tegra: vic: Support stream ID register programming Date: Fri, 1 Feb 2019 14:28:36 +0100 Message-Id: <20190201132837.12327-16-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190201132837.12327-1-thierry.reding@gmail.com> References: <20190201132837.12327-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The version of VIC found in Tegra186 and later incorporates improvements with regards to context isolation. As part of those improvements, stream ID registers were added that allow to specify separate stream IDs for the Falcon microcontroller and the VIC memory interface. While it is possible to also set the stream ID dynamically at runtime to allow userspace contexts to be completely separated, this commit doesn't implement that yet. Instead, the static VIC stream ID is programmed when the Falcon is booted. This ensures that memory accesses by the Falcon or the VIC are properly translated via the SMMU. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/vic.c | 21 +++++++++++++++++++++ drivers/gpu/drm/tegra/vic.h | 9 +++++++++ 2 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c index 55a8cc162e9d..aef8c16bfbee 100644 --- a/drivers/gpu/drm/tegra/vic.c +++ b/drivers/gpu/drm/tegra/vic.c @@ -26,6 +26,7 @@ struct vic_config { const char *firmware; unsigned int version; + bool supports_sid; }; struct vic { @@ -105,6 +106,22 @@ static int vic_boot(struct vic *vic) if (vic->booted) return 0; + if (vic->config->supports_sid) { + struct iommu_fwspec *spec = dev_iommu_fwspec_get(vic->dev); + u32 value; + + value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) | + TRANSCFG_ATT(0, TRANSCFG_SID_HW); + vic_writel(vic, value, VIC_TFBIF_TRANSCFG); + + if (spec->num_ids > 0) { + value = spec->ids[0] & 0xffff; + + vic_writel(vic, value, VIC_THI_STREAMID0); + vic_writel(vic, value, VIC_THI_STREAMID1); + } + } + /* setup clockgating registers */ vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) | CG_IDLE_CG_EN | @@ -314,6 +331,7 @@ static const struct tegra_drm_client_ops vic_ops = { static const struct vic_config vic_t124_config = { .firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE, .version = 0x40, + .supports_sid = false, }; #define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin" @@ -321,6 +339,7 @@ static const struct vic_config vic_t124_config = { static const struct vic_config vic_t210_config = { .firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE, .version = 0x21, + .supports_sid = false, }; #define NVIDIA_TEGRA_186_VIC_FIRMWARE "nvidia/tegra186/vic04_ucode.bin" @@ -328,6 +347,7 @@ static const struct vic_config vic_t210_config = { static const struct vic_config vic_t186_config = { .firmware = NVIDIA_TEGRA_186_VIC_FIRMWARE, .version = 0x18, + .supports_sid = true, }; #define NVIDIA_TEGRA_194_VIC_FIRMWARE "nvidia/tegra194/vic.bin" @@ -335,6 +355,7 @@ static const struct vic_config vic_t186_config = { static const struct vic_config vic_t194_config = { .firmware = NVIDIA_TEGRA_194_VIC_FIRMWARE, .version = 0x19, + .supports_sid = true, }; static const struct of_device_id vic_match[] = { diff --git a/drivers/gpu/drm/tegra/vic.h b/drivers/gpu/drm/tegra/vic.h index 21844817a7e1..017584340dd6 100644 --- a/drivers/gpu/drm/tegra/vic.h +++ b/drivers/gpu/drm/tegra/vic.h @@ -17,11 +17,20 @@ /* VIC registers */ +#define VIC_THI_STREAMID0 0x00000030 +#define VIC_THI_STREAMID1 0x00000034 + #define NV_PVIC_MISC_PRI_VIC_CG 0x000016d0 #define CG_IDLE_CG_DLY_CNT(val) ((val & 0x3f) << 0) #define CG_IDLE_CG_EN (1 << 6) #define CG_WAKEUP_DLY_CNT(val) ((val & 0xf) << 16) +#define VIC_TFBIF_TRANSCFG 0x00002044 +#define TRANSCFG_ATT(i, v) (((v) & 0x3) << (i * 4)) +#define TRANSCFG_SID_HW 0 +#define TRANSCFG_SID_PHY 1 +#define TRANSCFG_SID_FALCON 2 + /* Firmware offsets */ #define VIC_UCODE_FCE_HEADER_OFFSET (6*4)