From patchwork Fri Feb 1 03:43:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1034569 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="JOiNHoRV"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43rNHv1nrkz9s9G for ; Fri, 1 Feb 2019 14:43:55 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726557AbfBADny (ORCPT ); Thu, 31 Jan 2019 22:43:54 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:1104 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726488AbfBADnx (ORCPT ); Thu, 31 Jan 2019 22:43:53 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 31 Jan 2019 19:43:11 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 31 Jan 2019 19:43:53 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 31 Jan 2019 19:43:53 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 1 Feb 2019 03:43:51 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Fri, 1 Feb 2019 03:43:52 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 31 Jan 2019 19:43:51 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter CC: , , Joseph Lo Subject: [PATCH] arm64: dts: tegra210: Add L2 cache topology Date: Fri, 1 Feb 2019 11:43:47 +0800 Message-ID: <20190201034347.18470-1-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1548992591; bh=Tem64BNZk4Bo2XrHB+VOqJNn9yQCYOVq8Vn0A1BLLeU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: MIME-Version:X-NVConfidentiality:Content-Transfer-Encoding: Content-Type; b=JOiNHoRV3Lf5Unx8vl0wK+nV/uwxf6l0nUPlsiVwdPQkaERwrb+UrTOYl8KuKiX9k dANSzR+s1UTqyjRoEzEqbbAmUNQp2Xrb1b2KrWxjDgVhIQTP3yjlo18b22bbryUKjx WSfDGYqU0x6GPhBToioLojQRiLtRBaH6dlubVfl/ApNzwFJHP0njBMZ/ct0kPZyDU0 V1L+TauDh8eVMdkUkUOhsFJ/4UHNj9a93rf+XJ05B+i8JIQN3d9vc2yeNc+z+x/edo eEGqB27vpjA+OcnoObl1mBaSWzyFJ1TFfvoiuYkMaB38x//STubScIX5bJe0HkY2ke a8e8QfcIu2VMQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add L2 cache topology. Signed-off-by: Joseph Lo --- Notice that, This patch depends on the series of CPU idle support[1]. And that one depneds on [2]. [1]: http://patchwork.ozlabs.org/project/linux-tegra/list/?series=89446 [2]: http://patchwork.ozlabs.org/project/linux-tegra/list/?series=84380 --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 75534692604c..baf3d45c46e8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1319,6 +1319,7 @@ clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; clock-latency = <300000>; cpu-idle-states = <&C7>; + next-level-cache = <&L2>; }; cpu@1 { @@ -1326,6 +1327,7 @@ compatible = "arm,cortex-a57"; reg = <1>; cpu-idle-states = <&C7>; + next-level-cache = <&L2>; }; cpu@2 { @@ -1333,6 +1335,7 @@ compatible = "arm,cortex-a57"; reg = <2>; cpu-idle-states = <&C7>; + next-level-cache = <&L2>; }; cpu@3 { @@ -1340,6 +1343,7 @@ compatible = "arm,cortex-a57"; reg = <3>; cpu-idle-states = <&C7>; + next-level-cache = <&L2>; }; idle-states { @@ -1356,6 +1360,10 @@ status = "disabled"; }; }; + + L2: l2-cache { + compatible = "cache"; + }; }; timer {