arm64: dts: tegra210: Add L2 cache topology

Message ID 20190201034347.18470-1-josephl@nvidia.com
State Accepted
Headers show
Series
  • arm64: dts: tegra210: Add L2 cache topology
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Commit Message

Joseph Lo Feb. 1, 2019, 3:43 a.m.
Add L2 cache topology.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
Notice that,
This patch depends on the series of CPU idle support[1].
And that one depneds on [2].
[1]: http://patchwork.ozlabs.org/project/linux-tegra/list/?series=89446
[2]: http://patchwork.ozlabs.org/project/linux-tegra/list/?series=84380
---
 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Thierry Reding March 28, 2019, 4:10 p.m. | #1
On Fri, Feb 01, 2019 at 11:43:47AM +0800, Joseph Lo wrote:
> Add L2 cache topology.
> 
> Signed-off-by: Joseph Lo <josephl@nvidia.com>
> ---
> Notice that,
> This patch depends on the series of CPU idle support[1].
> And that one depneds on [2].
> [1]: http://patchwork.ozlabs.org/project/linux-tegra/list/?series=89446
> [2]: http://patchwork.ozlabs.org/project/linux-tegra/list/?series=84380
> ---
>  arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)

Applied to for-5.2/arm64/dt, thanks.

Thierry

Patch

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 75534692604c..baf3d45c46e8 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1319,6 +1319,7 @@ 
 			clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
 			clock-latency = <300000>;
 			cpu-idle-states = <&C7>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu@1 {
@@ -1326,6 +1327,7 @@ 
 			compatible = "arm,cortex-a57";
 			reg = <1>;
 			cpu-idle-states = <&C7>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu@2 {
@@ -1333,6 +1335,7 @@ 
 			compatible = "arm,cortex-a57";
 			reg = <2>;
 			cpu-idle-states = <&C7>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu@3 {
@@ -1340,6 +1343,7 @@ 
 			compatible = "arm,cortex-a57";
 			reg = <3>;
 			cpu-idle-states = <&C7>;
+			next-level-cache = <&L2>;
 		};
 
 		idle-states {
@@ -1356,6 +1360,10 @@ 
 				status = "disabled";
 			};
 		};
+
+		L2: l2-cache {
+			compatible = "cache";
+		};
 	};
 
 	timer {