From patchwork Wed Jul 6 10:28:31 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Weisser X-Patchwork-Id: 103453 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4F473B6F74 for ; Wed, 6 Jul 2011 20:30:16 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B3288280D1; Wed, 6 Jul 2011 12:29:41 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id riRoQxnr8F3k; Wed, 6 Jul 2011 12:29:41 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0F1EE280D2; Wed, 6 Jul 2011 12:29:24 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7A764280AB for ; Wed, 6 Jul 2011 12:29:20 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KfsjQ3t1p3Nt for ; Wed, 6 Jul 2011 12:29:19 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-in-10.arcor-online.net (mail-in-10.arcor-online.net [151.189.21.50]) by theia.denx.de (Postfix) with ESMTPS id 2254C280B1 for ; Wed, 6 Jul 2011 12:29:02 +0200 (CEST) Received: from mail-in-13-z2.arcor-online.net (mail-in-13-z2.arcor-online.net [151.189.8.30]) by mx.arcor.de (Postfix) with ESMTP id 873892D68F4; Wed, 6 Jul 2011 12:29:01 +0200 (CEST) Received: from mail-in-02.arcor-online.net (mail-in-02.arcor-online.net [151.189.21.42]) by mail-in-13-z2.arcor-online.net (Postfix) with ESMTP id 73E7CE19F0; Wed, 6 Jul 2011 12:29:01 +0200 (CEST) Received: from localhost.localdomain (unknown [212.87.136.142]) (Authenticated sender: weisserm@arcor.de) by mail-in-02.arcor-online.net (Postfix) with ESMTPA id C92C3305AF; Wed, 6 Jul 2011 12:28:57 +0200 (CEST) X-DKIM: Sendmail DKIM Filter v2.8.2 mail-in-02.arcor-online.net C92C3305AF From: Matthias Weisser To: u-boot@lists.denx.de Date: Wed, 6 Jul 2011 12:28:31 +0200 Message-Id: <1309948113-12971-5-git-send-email-weisserm@arcor.de> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1309427865-17531-1-git-send-email-weisserm@arcor.de> References: <1309427865-17531-1-git-send-email-weisserm@arcor.de> Subject: [U-Boot] [PATCH v2 4/6] imx: Add auto generation of asm-offsets.h for imx25 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Offsets to registers may be needed in asm code. This patch adds automated generation of these offsets form C structures. Signed-off-by: Matthias Weisser --- Changes in v2: - Added a change in Makefile which was in wrong patch of the patch set arch/arm/cpu/arm926ejs/mx25/Makefile | 2 + arch/arm/cpu/arm926ejs/mx25/asm-offsets.c | 60 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx25/imx-regs.h | 39 +++++++++++++++++++ 3 files changed, 101 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/mx25/asm-offsets.c diff --git a/arch/arm/cpu/arm926ejs/mx25/Makefile b/arch/arm/cpu/arm926ejs/mx25/Makefile index 3c2a65e..9219c06 100644 --- a/arch/arm/cpu/arm926ejs/mx25/Makefile +++ b/arch/arm/cpu/arm926ejs/mx25/Makefile @@ -34,6 +34,8 @@ all: $(obj).depend $(LIB) $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS)) +$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h + ######################################################################### # defines $(obj).depend target diff --git a/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c new file mode 100644 index 0000000..ba8dfd4 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c @@ -0,0 +1,60 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include + +#include + +int main(void) +{ + /* Clock Control Module */ + DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl)); + DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0)); + DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1)); + DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2)); + DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2])); + DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr)); + + /* Enhanced SDRAM Controller */ + DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0)); + DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0)); + DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc)); + + /* Multi-Layer AHB Crossbar Switch */ + DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); + DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); + DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); + DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); + DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); + DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); + DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); + DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); + DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); + DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); + DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); + DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); + DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); + DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); + DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); + + /* AHB <-> IP-Bus Interface */ + DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); + DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); + + return 0; +} diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index 55ad115..62ee4d5 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -141,6 +141,45 @@ struct fuse_bank0_regs { u32 mac_addr[6]; }; +/* Multi-Layer AHB Crossbar Switch (MAX) registers */ +struct max_regs { + u32 mpr0; + u32 pad00[3]; + u32 sgpcr0; + u32 pad01[59]; + u32 mpr1; + u32 pad02[3]; + u32 sgpcr1; + u32 pad03[59]; + u32 mpr2; + u32 pad04[3]; + u32 sgpcr2; + u32 pad05[59]; + u32 mpr3; + u32 pad06[3]; + u32 sgpcr3; + u32 pad07[59]; + u32 mpr4; + u32 pad08[3]; + u32 sgpcr4; + u32 pad09[251]; + u32 mgpcr0; + u32 pad10[63]; + u32 mgpcr1; + u32 pad11[63]; + u32 mgpcr2; + u32 pad12[63]; + u32 mgpcr3; + u32 pad13[63]; + u32 mgpcr4; +}; + +/* AHB <-> IP-Bus Interface (AIPS) */ +struct aips_regs { + u32 mpr_0_7; + u32 mpr_8_15; +}; + #endif /* AIPS 1 */