[PATCHv3,17/27] PCI: mobiveil: fix the checking of valid device

Message ID 20190129080926.36773-18-Zhiqiang.Hou@nxp.com
State Superseded
Delegated to: Lorenzo Pieralisi
Headers show
Series
  • PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs
Related show

Commit Message

Z.q. Hou Jan. 29, 2019, 8:10 a.m.
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Avoid to issue CFG transactions to link partner when the PCIe
link is not up. And allow CFG transactions to all functions of
Endpoint implemented multiple functions.

Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host
Bridge IP driver")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
V3:
 - No change

 drivers/pci/controller/mobiveil/pcie-mobiveil-host.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

Comments

Subrahmanya Lingappa Feb. 8, 2019, 12:41 p.m. | #1
ZQ,

On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
>
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> Avoid to issue CFG transactions to link partner when the PCIe
> link is not up. And allow CFG transactions to all functions of
> Endpoint implemented multiple functions.
>
> Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host
> Bridge IP driver")
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> ---
> V3:
>  - No change
>
>  drivers/pci/controller/mobiveil/pcie-mobiveil-host.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> index dc5324d94466..1ae82e790562 100644
> --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> @@ -29,6 +29,10 @@ static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
>  {
>         struct mobiveil_pcie *pcie = bus->sysdata;
>
> +       /* If there is no link, then there is no device */
> +       if (bus->number > pcie->rp.root_bus_nr && !mobiveil_pcie_link_up(pcie))
> +               return false;
> +
>         /* Only one device down on each root port */
>         if ((bus->number == pcie->rp.root_bus_nr) && (devfn > 0))
>                 return false;
> @@ -37,7 +41,7 @@ static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
>          * Do not read more than one device on the bus directly
>          * attached to RC
>          */
> -       if ((bus->primary == pcie->rp.root_bus_nr) && (devfn > 0))
> +       if ((bus->primary == pcie->rp.root_bus_nr) && (PCI_SLOT(devfn) > 0))
here change "primary" to "number", as it's a bug in the original driver too.

>                 return false;
>
>         return true;
> --
> 2.17.1
>
Bjorn Helgaas Feb. 8, 2019, 2:13 p.m. | #2
[+cc Thomas]

On Fri, Feb 08, 2019 at 06:11:15PM +0530, Subrahmanya Lingappa wrote:
> On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> >
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > Avoid to issue CFG transactions to link partner when the PCIe
> > link is not up. And allow CFG transactions to all functions of
> > Endpoint implemented multiple functions.
> >
> > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host
> > Bridge IP driver")
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > ---
> > V3:
> >  - No change
> >
> >  drivers/pci/controller/mobiveil/pcie-mobiveil-host.c | 6 +++++-
> >  1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> > index dc5324d94466..1ae82e790562 100644
> > --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> > +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> > @@ -29,6 +29,10 @@ static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
> >  {
> >         struct mobiveil_pcie *pcie = bus->sysdata;
> >
> > +       /* If there is no link, then there is no device */
> > +       if (bus->number > pcie->rp.root_bus_nr && !mobiveil_pcie_link_up(pcie))
> > +               return false;
> > +
> >         /* Only one device down on each root port */
> >         if ((bus->number == pcie->rp.root_bus_nr) && (devfn > 0))
> >                 return false;
> > @@ -37,7 +41,7 @@ static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
> >          * Do not read more than one device on the bus directly
> >          * attached to RC
> >          */
> > -       if ((bus->primary == pcie->rp.root_bus_nr) && (devfn > 0))
> > +       if ((bus->primary == pcie->rp.root_bus_nr) && (PCI_SLOT(devfn) > 0))

> here change "primary" to "number", as it's a bug in the original driver too.

This looks like it should be split into two patches: (1) checking for
link up, and (2) checking root_bus_nr.

And if you mean "bus->primary == pcie->rp.root_bus_nr" is a bug in
pci-aardvark.c, too, it is imperative to fix that bug also (with a
separate patch).

> >                 return false;
> >
> >         return true;
> > --
> > 2.17.1
> >
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Z.q. Hou Feb. 18, 2019, 7:04 a.m. | #3
Hi Subbu,

Thanks a lot for your comments!

> -----Original Message-----
> From: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> Sent: 2019年2月8日 20:41
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>;
> lorenzo.pieralisi@arm.com; catalin.marinas@arm.com;
> will.deacon@arm.com; Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv3 17/27] PCI: mobiveil: fix the checking of valid device
> 
> ZQ,
> 
> On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> >
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > Avoid to issue CFG transactions to link partner when the PCIe link is
> > not up. And allow CFG transactions to all functions of Endpoint
> > implemented multiple functions.
> >
> > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP
> > driver")
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > ---
> > V3:
> >  - No change
> >
> >  drivers/pci/controller/mobiveil/pcie-mobiveil-host.c | 6 +++++-
> >  1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> > b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> > index dc5324d94466..1ae82e790562 100644
> > --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> > +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> > @@ -29,6 +29,10 @@ static bool mobiveil_pcie_valid_device(struct
> > pci_bus *bus, unsigned int devfn)  {
> >         struct mobiveil_pcie *pcie = bus->sysdata;
> >
> > +       /* If there is no link, then there is no device */
> > +       if (bus->number > pcie->rp.root_bus_nr
> && !mobiveil_pcie_link_up(pcie))
> > +               return false;
> > +
> >         /* Only one device down on each root port */
> >         if ((bus->number == pcie->rp.root_bus_nr) && (devfn > 0))
> >                 return false;
> > @@ -37,7 +41,7 @@ static bool mobiveil_pcie_valid_device(struct pci_bus
> *bus, unsigned int devfn)
> >          * Do not read more than one device on the bus directly
> >          * attached to RC
> >          */
> > -       if ((bus->primary == pcie->rp.root_bus_nr) && (devfn > 0))
> > +       if ((bus->primary == pcie->rp.root_bus_nr) && (PCI_SLOT(devfn)
> > + > 0))
> here change "primary" to "number", as it's a bug in the original driver too.

No, I think it should not change to "number", as this is to check the EP directly attached to RC, so if we change it to "bus->number", the "pcie->rp.root_bus_nr" should be changed to "pcie->rp.root_bus_nr +1" correspondingly.

> 
> >                 return false;
> >
> >         return true;
> > --
> > 2.17.1
> >

Thanks,
Zhiqiang
Z.q. Hou Feb. 18, 2019, 7:15 a.m. | #4
Hi Bjorn,

Thanks a lot for your comments!

> -----Original Message-----
> From: Bjorn Helgaas <helgaas@kernel.org>
> Sent: 2019年2月8日 22:13
> To: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> Cc: Z.q. Hou <zhiqiang.hou@nxp.com>; mark.rutland@arm.com;
> devicetree@vger.kernel.org; lorenzo.pieralisi@arm.com; Xiaowei Bao
> <xiaowei.bao@nxp.com>; linux-pci@vger.kernel.org; will.deacon@arm.com;
> linux-kernel@vger.kernel.org; Leo Li <leoyang.li@nxp.com>; M.h. Lian
> <minghuan.lian@nxp.com>; robh+dt@kernel.org; Mingkai Hu
> <mingkai.hu@nxp.com>; catalin.marinas@arm.com; shawnguo@kernel.org;
> linux-arm-kernel@lists.infradead.org; Thomas Petazzoni
> <thomas.petazzoni@bootlin.com>
> Subject: Re: [PATCHv3 17/27] PCI: mobiveil: fix the checking of valid device
> 
> [+cc Thomas]
> 
> On Fri, Feb 08, 2019 at 06:11:15PM +0530, Subrahmanya Lingappa wrote:
> > On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> > >
> > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > >
> > > Avoid to issue CFG transactions to link partner when the PCIe link
> > > is not up. And allow CFG transactions to all functions of Endpoint
> > > implemented multiple functions.
> > >
> > > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge
> > > IP driver")
> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > > ---
> > > V3:
> > >  - No change
> > >
> > >  drivers/pci/controller/mobiveil/pcie-mobiveil-host.c | 6 +++++-
> > >  1 file changed, 5 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> > > b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> > > index dc5324d94466..1ae82e790562 100644
> > > --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> > > +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> > > @@ -29,6 +29,10 @@ static bool mobiveil_pcie_valid_device(struct
> > > pci_bus *bus, unsigned int devfn)  {
> > >         struct mobiveil_pcie *pcie = bus->sysdata;
> > >
> > > +       /* If there is no link, then there is no device */
> > > +       if (bus->number > pcie->rp.root_bus_nr
> && !mobiveil_pcie_link_up(pcie))
> > > +               return false;
> > > +
> > >         /* Only one device down on each root port */
> > >         if ((bus->number == pcie->rp.root_bus_nr) && (devfn > 0))
> > >                 return false;
> > > @@ -37,7 +41,7 @@ static bool mobiveil_pcie_valid_device(struct
> pci_bus *bus, unsigned int devfn)
> > >          * Do not read more than one device on the bus directly
> > >          * attached to RC
> > >          */
> > > -       if ((bus->primary == pcie->rp.root_bus_nr) && (devfn > 0))
> > > +       if ((bus->primary == pcie->rp.root_bus_nr) &&
> > > + (PCI_SLOT(devfn) > 0))
> 
> > here change "primary" to "number", as it's a bug in the original driver too.
> 
> This looks like it should be split into two patches: (1) checking for link up, and
> (2) checking root_bus_nr.

Yes, will split this patch in next version.

> 
> And if you mean "bus->primary == pcie->rp.root_bus_nr" is a bug in
> pci-aardvark.c, too, it is imperative to fix that bug also (with a separate patch).

It is not a bug, but the bug is to limit multiple function EP (devfn > 0).

Thanks,
Zhiqiang

Patch

diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
index dc5324d94466..1ae82e790562 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
@@ -29,6 +29,10 @@  static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
 {
 	struct mobiveil_pcie *pcie = bus->sysdata;
 
+	/* If there is no link, then there is no device */
+	if (bus->number > pcie->rp.root_bus_nr && !mobiveil_pcie_link_up(pcie))
+		return false;
+
 	/* Only one device down on each root port */
 	if ((bus->number == pcie->rp.root_bus_nr) && (devfn > 0))
 		return false;
@@ -37,7 +41,7 @@  static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
 	 * Do not read more than one device on the bus directly
 	 * attached to RC
 	 */
-	if ((bus->primary == pcie->rp.root_bus_nr) && (devfn > 0))
+	if ((bus->primary == pcie->rp.root_bus_nr) && (PCI_SLOT(devfn) > 0))
 		return false;
 
 	return true;