[1/3] linux-user:Support for MIPS64 user mode emulation in QEMU

diff --git a/configure b/configure
index 88159ac..ad4c321 100755
--- a/configure
+++ b/configure
@@ -866,6 +866,7 @@  m68k-linux-user \
 microblaze-linux-user \
 microblazeel-linux-user \
 mips-linux-user \
+mips64-linux-user \
 mipsel-linux-user \
 ppc-linux-user \
 ppc64-linux-user \
diff --git a/default-configs/mips64-linux-user.mak b/default-configs/mips64-linux-user.mak
new file mode 100644
index 0000000..1598bfc
--- /dev/null
+++ b/default-configs/mips64-linux-user.mak
@@ -0,0 +1 @@ 
+# Default configuration for mips64-linux-user
diff --git a/linux-user/main.c b/linux-user/main.c
index 289054b..a3ed752 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -2041,7 +2041,8 @@  static int do_store_exclusive(CPUMIPSState *env)
 void cpu_loop(CPUMIPSState *env)
 {
     target_siginfo_t info;
-    int trapnr, ret;
+    int trapnr;
+    abi_long ret;
     unsigned int syscall_num;
 
     for(;;) {
@@ -2050,8 +2051,23 @@  void cpu_loop(CPUMIPSState *env)
         cpu_exec_end(env);
         switch(trapnr) {
         case EXCP_SYSCALL:
-            syscall_num = env->active_tc.gpr[2] - 4000;
             env->active_tc.PC += 4;
+#if defined(TARGET_MIPS64)
+            syscall_num = env->active_tc.gpr[2] - 5000;
+            /* MIPS64 has eight argument registers so there is
+             * no need to get arguments from stack
+             */
+            ret = do_syscall(env, env->active_tc.gpr[2],
+                             env->active_tc.gpr[4],
+                             env->active_tc.gpr[5],
+                             env->active_tc.gpr[6],
+                             env->active_tc.gpr[7],
+                             env->active_tc.gpr[8],
+                             env->active_tc.gpr[9],
+                             env->active_tc.gpr[10],
+                             env->active_tc.gpr[11]);
+#else
+            syscall_num = env->active_tc.gpr[2] - 4000;
             if (syscall_num >= sizeof(mips_syscall_args)) {
                 ret = -ENOSYS;
             } else {
@@ -2078,6 +2094,7 @@  void cpu_loop(CPUMIPSState *env)
                                  env->active_tc.gpr[7],
                                  arg5, arg6, arg7, arg8);
             }
+#endif
             if (ret == -TARGET_QEMU_ESIGRETURN) {
                 /* Returning from a successful sigreturn syscall.
                    Avoid clobbering register state.  */
diff --git a/linux-user/mips64/syscall.h b/linux-user/mips64/syscall.h
index 668a2b9..96f03da 100644
--- a/linux-user/mips64/syscall.h
+++ b/linux-user/mips64/syscall.h
@@ -218,4 +218,6 @@  struct target_pt_regs {
 
 
 
+#define TARGET_QEMU_ESIGRETURN 255
+
 #define UNAME_MACHINE "mips64"
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 7d168e1..48a22e0 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -2414,8 +2414,8 @@  void sparc64_get_context(CPUSPARCState *env)
 }
 #endif
 #elif defined(TARGET_ABI_MIPSN64)
-
-# warning signal handling not implemented
+/* Signal handling will be Implemented soon
+# warning signal handling not implemented */
 
 static void setup_frame(int sig, struct target_sigaction *ka,
 			target_sigset_t *set, CPUState *env)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index fed7a8f..339dede 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -7584,6 +7584,11 @@  abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
     case TARGET_NR_set_thread_area:
 #if defined(TARGET_MIPS)
       ((CPUMIPSState *) cpu_env)->tls_value = arg1;
+      if (((CPUMIPSState *) cpu_env)->insn_flags & CPU_OCTEON) {
+          /* tls entry is moved to k0 so that this can be used later
+             currently this thing is tested only for Octeon */
+          ((CPUMIPSState *) cpu_env)->active_tc.gpr[26] = arg1;
+      }
       ret = 0;
       break;
 #elif defined(TARGET_CRIS)