From patchwork Fri Jan 25 11:25:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1031013 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ReOvbQCo"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43mGt92mJ5z9s9h for ; Fri, 25 Jan 2019 22:25:53 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727097AbfAYLZe (ORCPT ); Fri, 25 Jan 2019 06:25:34 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:36677 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726126AbfAYLZb (ORCPT ); Fri, 25 Jan 2019 06:25:31 -0500 Received: by mail-wm1-f65.google.com with SMTP id p6so6282924wmc.1; Fri, 25 Jan 2019 03:25:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/Z8HJRf7jFWL8ndlHDECsk1rDr2pU3ULSQ2VkFakbVM=; b=ReOvbQCoTIwL8WRPo12puX+FLVBg9muumJqmo4+OeXl0dFx9DKt/KoLL6v+zIBXfYo 6Ix8ZPu6YwZYBx4gmQZ2Qk2MymHfjuh/IBl6gV2zDG9aofAV0AZqKLt4rxTrVetzodmt 1xlSs5mvRtCjlz4Hoo5CFpwvdi+bpiiUXkXLg3bWtSG8z3zG+gIylRGguK65Y3tje1Uz BwHoD54qhM0wb5GPElmUf/uSSOvCZyp7bZirDxw8pTJlARCbjPW5NZiMZlomkhj3cOkE lSYyLO08slesdxcYuqFJRyKv1ILMMgnR3WYbHeHzbAA1VY+57xt8HcF1K7GcV5w/1n0f A3nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/Z8HJRf7jFWL8ndlHDECsk1rDr2pU3ULSQ2VkFakbVM=; b=mgqB3prKLx5/K3hboySQ314H26epxBOvN9XJ8j6+GwMIEAtsNzpfnhkHZzoDTRqBfO +hFmixPBxgKE1cN0sYPjN5BOuKERCOcwMzPeNZsQz+WF4Q2lKMsyo/N5NCA03jObOjd7 TFABF6wAqaUkMOXmTgzulLStnCmc1qIQmqMsBiYug8DdcRbXRpzXRm2gwiVaetYullSA 8ODDIn1x4H001o7x7q805Y8J2xQNNCmlZypLE8W7cFJEr2oKvj2IECI8RnwmR+tZ4SDk DwWlqyVUsk1iRPbhCZcCSsqwhiCwsh2rPTMyg8aTJv8YiLmyYKoTrt4OI944xIHnlBWj mn4g== X-Gm-Message-State: AJcUukck0hLUDs4WV91Lov0dydd7j6uolOHQS+ETecX4ZGJtzd59jL/w Z2qV8a8mkRQlVT5JZRe1iMQ= X-Google-Smtp-Source: ALg8bN4bYifcjefhPEJ33UuhPbDKkSL8TRnkCqJK/Hp10GVaNvIzzHYvK/iDXqw6jhU8XNRCwROvuw== X-Received: by 2002:a1c:1688:: with SMTP id 130mr6261924wmw.86.1548415529596; Fri, 25 Jan 2019 03:25:29 -0800 (PST) Received: from localhost (pD9E51040.dip0.t-ipconnect.de. [217.229.16.64]) by smtp.gmail.com with ESMTPSA id a187sm57523034wmf.33.2019.01.25.03.25.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jan 2019 03:25:28 -0800 (PST) From: Thierry Reding To: Kishon Vijay Abraham I Cc: Jonathan Hunter , JC Kuo , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/5] phy: tegra: xusb: Skip single function lane programming Date: Fri, 25 Jan 2019 12:25:22 +0100 Message-Id: <20190125112525.10697-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190125112525.10697-1-thierry.reding@gmail.com> References: <20190125112525.10697-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: JC Kuo Tegra186 USB2 pads and USB3 pads do not have hardware mux for changing the pad function. For such "lanes", we can skip the lane mux register programming. Signed-off-by: JC Kuo Signed-off-by: Thierry Reding Reviewed-by: JC Kuo --- drivers/phy/tegra/xusb.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c index 5b3b8863363e..e3bc60cfe6a1 100644 --- a/drivers/phy/tegra/xusb.c +++ b/drivers/phy/tegra/xusb.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -313,6 +313,10 @@ static void tegra_xusb_lane_program(struct tegra_xusb_lane *lane) const struct tegra_xusb_lane_soc *soc = lane->soc; u32 value; + /* skip single function lanes */ + if (soc->num_funcs < 2) + return; + /* choose function */ value = padctl_readl(padctl, soc->offset); value &= ~(soc->mask << soc->shift);