From patchwork Tue Jan 22 15:59:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ram Pai X-Patchwork-Id: 1029371 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43kY6k44Wkz9s9G for ; Wed, 23 Jan 2019 03:00:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728822AbfAVQAq (ORCPT ); Tue, 22 Jan 2019 11:00:46 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:40918 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728784AbfAVQAq (ORCPT ); Tue, 22 Jan 2019 11:00:46 -0500 Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x0MFvan8040761 for ; Tue, 22 Jan 2019 11:00:44 -0500 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2q6421y7yd-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 22 Jan 2019 11:00:43 -0500 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 22 Jan 2019 16:00:38 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0MG0S8n39059614 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Jan 2019 16:00:28 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 80A9BA405B; Tue, 22 Jan 2019 16:00:27 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 66C3CA405E; Tue, 22 Jan 2019 16:00:23 +0000 (GMT) Received: from ram.ibm.com (unknown [9.85.201.166]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 22 Jan 2019 16:00:23 +0000 (GMT) From: Ram Pai To: kvm-ppc@vger.kernel.org Cc: cclaudio@br.ibm.com, maddy@linux.vnet.ibm.com, rgrimm@us.ibm.com, pmac@au1.ibm.com, andmike@us.ibm.com, sukadev@linux.vnet.ibm.com, bauerman@linux.ibm.com, santosh@linux.ibm.com, benh@linux.ibm.com, sesmith@au1.ibm.com, bharata@linux.ibm.com Subject: [PATCH 04/13] KVM: PPC: Ultravisor: Use UV_WRITE_PATE ucall to register a PATE Date: Tue, 22 Jan 2019 07:59:35 -0800 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1548172784-27414-4-git-send-email-linuxram@us.ibm.com> References: <1548172784-27414-1-git-send-email-linuxram@us.ibm.com> <1548172784-27414-2-git-send-email-linuxram@us.ibm.com> <1548172784-27414-3-git-send-email-linuxram@us.ibm.com> <1548172784-27414-4-git-send-email-linuxram@us.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19012216-0008-0000-0000-000002B476A8 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19012216-0009-0000-0000-00002220A351 Message-Id: <1548172784-27414-5-git-send-email-linuxram@us.ibm.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-22_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901220124 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Michael Anderson The Nest_MMU needs to know the address of the Partition table (PT). However the PT is in secure memory, and nestMMU cannot access secure memory. Hence hypevisor will continue to use a Partition table of its own. It will have PATE entries for HV and for Normal virtual machines. The same entries are also in the UV's PT. The HV's PT is programmed with the nest MMU. Suggested-by: Ryan Grimm Signed-off-by: Madhavan Srinivasan [device node name to ibm,ultravisor] Signed-off-by: Michael Anderson Signed-off-by: Ram Pai --- arch/powerpc/include/asm/ucall-api.h | 30 +++++++++++++++++++++++++++++ arch/powerpc/include/uapi/asm/uapi_uvcall.h | 2 ++ arch/powerpc/mm/hash_utils_64.c | 4 +++- arch/powerpc/mm/pgtable-book3s64.c | 29 ++++++++++++++++++++++++++-- arch/powerpc/mm/pgtable-radix.c | 10 +++++++--- 5 files changed, 69 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/include/asm/ucall-api.h b/arch/powerpc/include/asm/ucall-api.h index 3833b55..f411dcb 100644 --- a/arch/powerpc/include/asm/ucall-api.h +++ b/arch/powerpc/include/asm/ucall-api.h @@ -1,5 +1,35 @@ /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_POWERPC_UCALL_API_H #define _ASM_POWERPC_UCALL_API_H + #include + +#ifndef __ASSEMBLY__ + +#include +#include + +extern unsigned int smf_state; +static inline bool smf_enabled(void) +{ + unsigned long smf; + + if (!smf_state) { + smf = of_get_flat_dt_subnode_by_name(0, "ibm,ultravisor"); + smf_state = (smf == -FDT_ERR_NOTFOUND) ? 1 : 2; + } + return (smf_state == 2); +} + +#define PLPAR_UCALL_BUFSIZE 4 +long plpar_ucall(unsigned long opcode, unsigned long *retbuf, ...); + +static inline int uv_register_pate(u64 lpid, u64 dw0, u64 dw1) +{ + unsigned long retbuf[PLPAR_UCALL_BUFSIZE]; + + return plpar_ucall(UV_WRITE_PATE, retbuf, lpid, dw0, dw1); +} + +#endif /* __ASSEMBLY__ */ #endif /* _ASM_POWERPC_UCALL_API_H */ diff --git a/arch/powerpc/include/uapi/asm/uapi_uvcall.h b/arch/powerpc/include/uapi/asm/uapi_uvcall.h index 7e213a1..7f018cf 100644 --- a/arch/powerpc/include/uapi/asm/uapi_uvcall.h +++ b/arch/powerpc/include/uapi/asm/uapi_uvcall.h @@ -7,4 +7,6 @@ */ #ifndef UAPI_UC_H #define UAPI_UC_H + +#define UV_WRITE_PATE 0xf104 #endif /* #ifndef UAPI_UC_H */ diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c index 0cc7fbc..6d0eef6 100644 --- a/arch/powerpc/mm/hash_utils_64.c +++ b/arch/powerpc/mm/hash_utils_64.c @@ -64,6 +64,7 @@ #include #include #include +#include #ifdef DEBUG #define DBG(fmt...) udbg_printf(fmt) @@ -1051,9 +1052,10 @@ void hash__early_init_mmu_secondary(void) if (!cpu_has_feature(CPU_FTR_ARCH_300)) mtspr(SPRN_SDR1, _SDR1); - else + else if (!smf_enabled()) mtspr(SPRN_PTCR, __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); + } /* Initialize SLB */ slb_initialize(); diff --git a/arch/powerpc/mm/pgtable-book3s64.c b/arch/powerpc/mm/pgtable-book3s64.c index f3c31f5..ba6b34d 100644 --- a/arch/powerpc/mm/pgtable-book3s64.c +++ b/arch/powerpc/mm/pgtable-book3s64.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "mmu_decl.h" #include @@ -206,11 +207,23 @@ void __init mmu_partition_table_init(void) * 64 K size. */ ptcr = __pa(partition_tb) | (PATB_SIZE_SHIFT - 12); - mtspr(SPRN_PTCR, ptcr); + /* + * Ultravisor creates and manages partition table if SMF + * is enabled. + */ + if (!smf_enabled()) + mtspr(SPRN_PTCR, ptcr); + + /* + * Since nestMMU cannot access secure memory. Create + * and manage our own partition table. This table + * contains entries for nonsecure and hypervisor + * partition. + */ powernv_set_nmmu_ptcr(ptcr); } -void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0, +static void __mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0, unsigned long dw1) { unsigned long old = be64_to_cpu(partition_tb[lpid].patb0); @@ -238,6 +251,18 @@ void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0, /* do we need fixup here ?*/ asm volatile("eieio; tlbsync; ptesync" : : : "memory"); } + +void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0, + unsigned long dw1) +{ + pr_info("%s: SMF Regitered PATE for Hypervisor dw0 = 0x%lx dw1 = 0x%lx ", __func__, dw0, dw1); + if (smf_enabled()) + uv_register_pate(lpid, dw0, dw1); + + __mmu_partition_table_set_entry(lpid, dw0, dw1); + return; +} + EXPORT_SYMBOL_GPL(mmu_partition_table_set_entry); static pmd_t *get_pmd_from_cache(struct mm_struct *mm) diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c index 9311560..bcc8398 100644 --- a/arch/powerpc/mm/pgtable-radix.c +++ b/arch/powerpc/mm/pgtable-radix.c @@ -29,11 +29,13 @@ #include #include #include +#include #include unsigned int mmu_pid_bits; unsigned int mmu_base_pid; +unsigned int smf_state; static int native_register_process_table(unsigned long base, unsigned long pg_sz, unsigned long table_size) @@ -623,8 +625,9 @@ void radix__early_init_mmu_secondary(void) lpcr = mfspr(SPRN_LPCR); mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR); - mtspr(SPRN_PTCR, - __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); + if (!smf_enabled()) + mtspr(SPRN_PTCR, __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); + radix_init_amor(); } radix_init_iamr(); @@ -641,7 +644,8 @@ void radix__mmu_cleanup_all(void) if (!firmware_has_feature(FW_FEATURE_LPAR)) { lpcr = mfspr(SPRN_LPCR); mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT); - mtspr(SPRN_PTCR, 0); + if (!smf_enabled()) + mtspr(SPRN_PTCR, 0); powernv_set_nmmu_ptcr(0); radix__flush_tlb_all(); }