[03/13] KVM: PPC: Ultravisor: Introduce the MSR_S bit
diff mbox series

Message ID 1548172784-27414-4-git-send-email-linuxram@us.ibm.com
State Changes Requested
Headers show
Series
  • KVM: PPC: Paravirtualize KVM to support Ultravisor
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Commit Message

Ram Pai Jan. 22, 2019, 3:59 p.m. UTC
From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>

MSR_S bit enables access to secure memory.

Signed-off-by: Ram Pai <linuxram@us.ibm.com>
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
---
 arch/powerpc/include/asm/reg.h | 3 +++
 1 file changed, 3 insertions(+)

Comments

Paul Mackerras Jan. 22, 2019, 11:36 p.m. UTC | #1
On Tue, Jan 22, 2019 at 07:59:34AM -0800, Ram Pai wrote:
> From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
> 
> MSR_S bit enables access to secure memory.

I would like to see a bit more commentary here that explains that the
hypervisor doesn't (and can't) run with the MSR_S bit set, but a
secure guest and the ultravisor do.

> Signed-off-by: Ram Pai <linuxram@us.ibm.com>
> Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>

Nit: signoffs are in the wrong order.

Paul.

Patch
diff mbox series

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 1c98ef1..3c3588a 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -38,6 +38,7 @@ 
 #define MSR_TM_LG	32		/* Trans Mem Available */
 #define MSR_VEC_LG	25	        /* Enable AltiVec */
 #define MSR_VSX_LG	23		/* Enable VSX */
+#define MSR_S_LG	22		/* Secure VM bit */
 #define MSR_POW_LG	18		/* Enable Power Management */
 #define MSR_WE_LG	18		/* Wait State Enable */
 #define MSR_TGPR_LG	17		/* TLB Update registers in use */
@@ -71,11 +72,13 @@ 
 #define MSR_SF		__MASK(MSR_SF_LG)	/* Enable 64 bit mode */
 #define MSR_ISF		__MASK(MSR_ISF_LG)	/* Interrupt 64b mode valid on 630 */
 #define MSR_HV 		__MASK(MSR_HV_LG)	/* Hypervisor state */
+#define MSR_S 		__MASK(MSR_S_LG)	/* Secure state */
 #else
 /* so tests for these bits fail on 32-bit */
 #define MSR_SF		0
 #define MSR_ISF		0
 #define MSR_HV		0
+#define MSR_S		0
 #endif
 
 /*