[2/4] pwm: atmel: add support for controllers with 32 bit counters
diff mbox series

Message ID 1548073783-22640-3-git-send-email-claudiu.beznea@microchip.com
State Superseded
Headers show
Series
  • add support for the new SAM9X60's PWM controller
Related show

Commit Message

Claudiu Beznea Jan. 21, 2019, 12:30 p.m. UTC
From: Claudiu Beznea <claudiu.beznea@microchip.com>

New SAM9X60's PWM controller use 32 bits counters thus it could generate
signals with higher period and duty cycles. Update the current driver
to work with old controller (that uses 16 bits counters) and with the
new SAM9X60's controller.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 drivers/pwm/pwm-atmel.c | 38 +++++++++++++++++++++++++++-----------
 1 file changed, 27 insertions(+), 11 deletions(-)

Comments

Uwe Kleine-König Feb. 19, 2019, 7:42 a.m. UTC | #1
Hello Claudiu,

On Mon, Jan 21, 2019 at 12:30:53PM +0000, Claudiu.Beznea@microchip.com wrote:
> From: Claudiu Beznea <claudiu.beznea@microchip.com>
> 
> New SAM9X60's PWM controller use 32 bits counters thus it could generate
> signals with higher period and duty cycles. Update the current driver
> to work with old controller (that uses 16 bits counters) and with the
> new SAM9X60's controller.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
>  drivers/pwm/pwm-atmel.c | 38 +++++++++++++++++++++++++++-----------
>  1 file changed, 27 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c
> index 7e86a5266eb6..44f4a1c9f60b 100644
> --- a/drivers/pwm/pwm-atmel.c
> +++ b/drivers/pwm/pwm-atmel.c
> @@ -48,15 +48,15 @@
>  #define PWMV2_CPRD		0x0C
>  #define PWMV2_CPRDUPD		0x10
>  
> -/*
> - * Max value for duty and period
> - *
> - * Although the duty and period register is 32 bit,
> - * however only the LSB 16 bits are significant.
> - */
> -#define PWM_MAX_DTY		0xFFFF
> -#define PWM_MAX_PRD		0xFFFF
> -#define PRD_MAX_PRES		10
> +/* Max values for period and prescaler */
> +
> +/* Only the LSB 16 bits are significant. */
> +#define PWM_MAXV1_PRD		0xFFFF
> +
> +/* All 32 bits are significant. */
> +#define PWM_MAXV2_PRD		0xFFFFFFFF

This symbol is unused, so I wonder if the patch really does what the
commit log promises.

Best regards
Uwe
Claudiu Beznea Feb. 19, 2019, 8:57 a.m. UTC | #2
On 19.02.2019 09:42, Uwe Kleine-König wrote:
> Hello Claudiu,
> 
> On Mon, Jan 21, 2019 at 12:30:53PM +0000, Claudiu.Beznea@microchip.com wrote:
>> From: Claudiu Beznea <claudiu.beznea@microchip.com>
>>
>> New SAM9X60's PWM controller use 32 bits counters thus it could generate
>> signals with higher period and duty cycles. Update the current driver
>> to work with old controller (that uses 16 bits counters) and with the
>> new SAM9X60's controller.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>> ---
>>  drivers/pwm/pwm-atmel.c | 38 +++++++++++++++++++++++++++-----------
>>  1 file changed, 27 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c
>> index 7e86a5266eb6..44f4a1c9f60b 100644
>> --- a/drivers/pwm/pwm-atmel.c
>> +++ b/drivers/pwm/pwm-atmel.c
>> @@ -48,15 +48,15 @@
>>  #define PWMV2_CPRD		0x0C
>>  #define PWMV2_CPRDUPD		0x10
>>  
>> -/*
>> - * Max value for duty and period
>> - *
>> - * Although the duty and period register is 32 bit,
>> - * however only the LSB 16 bits are significant.
>> - */
>> -#define PWM_MAX_DTY		0xFFFF
>> -#define PWM_MAX_PRD		0xFFFF
>> -#define PRD_MAX_PRES		10
>> +/* Max values for period and prescaler */
>> +
>> +/* Only the LSB 16 bits are significant. */
>> +#define PWM_MAXV1_PRD		0xFFFF
>> +
>> +/* All 32 bits are significant. */
>> +#define PWM_MAXV2_PRD		0xFFFFFFFF
> 
> This symbol is unused, so I wonder if the patch really does what the
> commit log promises.

It is only of SAM9X60's PWM. Please check patch 3/4. Maybe I should have
been introduced it in there. If you consider it is better to be introduced
in patch 3/4 please let me know.

> 
> Best regards
> Uwe
>
Uwe Kleine-König Feb. 19, 2019, 9:15 a.m. UTC | #3
On Tue, Feb 19, 2019 at 08:57:04AM +0000, Claudiu.Beznea@microchip.com wrote:
> 
> 
> On 19.02.2019 09:42, Uwe Kleine-König wrote:
> > Hello Claudiu,
> > 
> > On Mon, Jan 21, 2019 at 12:30:53PM +0000, Claudiu.Beznea@microchip.com wrote:
> >> From: Claudiu Beznea <claudiu.beznea@microchip.com>
> >>
> >> New SAM9X60's PWM controller use 32 bits counters thus it could generate
> >> signals with higher period and duty cycles. Update the current driver
> >> to work with old controller (that uses 16 bits counters) and with the
> >> new SAM9X60's controller.
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> >> ---
> >>  drivers/pwm/pwm-atmel.c | 38 +++++++++++++++++++++++++++-----------
> >>  1 file changed, 27 insertions(+), 11 deletions(-)
> >>
> >> diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c
> >> index 7e86a5266eb6..44f4a1c9f60b 100644
> >> --- a/drivers/pwm/pwm-atmel.c
> >> +++ b/drivers/pwm/pwm-atmel.c
> >> @@ -48,15 +48,15 @@
> >>  #define PWMV2_CPRD		0x0C
> >>  #define PWMV2_CPRDUPD		0x10
> >>  
> >> -/*
> >> - * Max value for duty and period
> >> - *
> >> - * Although the duty and period register is 32 bit,
> >> - * however only the LSB 16 bits are significant.
> >> - */
> >> -#define PWM_MAX_DTY		0xFFFF
> >> -#define PWM_MAX_PRD		0xFFFF
> >> -#define PRD_MAX_PRES		10
> >> +/* Max values for period and prescaler */
> >> +
> >> +/* Only the LSB 16 bits are significant. */
> >> +#define PWM_MAXV1_PRD		0xFFFF
> >> +
> >> +/* All 32 bits are significant. */
> >> +#define PWM_MAXV2_PRD		0xFFFFFFFF
> > 
> > This symbol is unused, so I wonder if the patch really does what the
> > commit log promises.
> 
> It is only of SAM9X60's PWM. Please check patch 3/4. Maybe I should have
> been introduced it in there. If you consider it is better to be introduced
> in patch 3/4 please let me know.

Yeah, I think cpp symbols should be introduced with their first user.
And then the commit log should read something like:

	New SAM9X60's PWM controller use 32 bits counters thus it could
	generate signals with higher period and duty cycles compared to
	the already supported implementations that only have 16 bit
	counters. Update the driver to handle counter width depending on
	compatible data. Semantically this is a no-op but it's used in
	the next patch to add support for SAM9X60.

Best regards
Uwe

Patch
diff mbox series

diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c
index 7e86a5266eb6..44f4a1c9f60b 100644
--- a/drivers/pwm/pwm-atmel.c
+++ b/drivers/pwm/pwm-atmel.c
@@ -48,15 +48,15 @@ 
 #define PWMV2_CPRD		0x0C
 #define PWMV2_CPRDUPD		0x10
 
-/*
- * Max value for duty and period
- *
- * Although the duty and period register is 32 bit,
- * however only the LSB 16 bits are significant.
- */
-#define PWM_MAX_DTY		0xFFFF
-#define PWM_MAX_PRD		0xFFFF
-#define PRD_MAX_PRES		10
+/* Max values for period and prescaler */
+
+/* Only the LSB 16 bits are significant. */
+#define PWM_MAXV1_PRD		0xFFFF
+
+/* All 32 bits are significant. */
+#define PWM_MAXV2_PRD		0xFFFFFFFF
+
+#define PRD_MAXV1_PRES		10
 
 struct atmel_pwm_registers {
 	u8 period;
@@ -65,8 +65,14 @@  struct atmel_pwm_registers {
 	u8 duty_upd;
 };
 
+struct atmel_pwm_config {
+	u32 max_period;
+	u32 max_pres;
+};
+
 struct atmel_pwm_data {
 	struct atmel_pwm_registers regs;
+	struct atmel_pwm_config cfg;
 };
 
 struct atmel_pwm_chip {
@@ -125,10 +131,10 @@  static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
 	cycles *= clk_get_rate(atmel_pwm->clk);
 	do_div(cycles, NSEC_PER_SEC);
 
-	for (*pres = 0; cycles > PWM_MAX_PRD; cycles >>= 1)
+	for (*pres = 0; cycles > atmel_pwm->data->cfg.max_period; cycles >>= 1)
 		(*pres)++;
 
-	if (*pres > PRD_MAX_PRES) {
+	if (*pres > atmel_pwm->data->cfg.max_pres) {
 		dev_err(chip->dev, "pres exceeds the maximum value\n");
 		return -EINVAL;
 	}
@@ -288,6 +294,11 @@  static const struct atmel_pwm_data atmel_pwm_data_v1 = {
 		.duty		= PWMV1_CDTY,
 		.duty_upd	= PWMV1_CUPD,
 	},
+	.cfg = {
+		/* 16 bits to keep period and duty. */
+		.max_period	= PWM_MAXV1_PRD,
+		.max_pres	= PRD_MAXV1_PRES,
+	},
 };
 
 static const struct atmel_pwm_data atmel_pwm_data_v2 = {
@@ -297,6 +308,11 @@  static const struct atmel_pwm_data atmel_pwm_data_v2 = {
 		.duty		= PWMV2_CDTY,
 		.duty_upd	= PWMV2_CDTYUPD,
 	},
+	.cfg = {
+		/* 16 bits to keep period and duty. */
+		.max_period	= PWM_MAXV1_PRD,
+		.max_pres	= PRD_MAXV1_PRES,
+	},
 };
 
 static const struct platform_device_id atmel_pwm_devtypes[] = {