| Message ID | 20190113185842.1410-3-simon.k.r.goldschmidt@gmail.com |
|---|---|
| State | Accepted, archived |
| Commit | 6fb1eb1b7642d0d4dc984bc087939fb40142754c |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | arm: socpfpga: gen5 clean up ETH RST & PHY mode | expand |
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index b7c0b921e6..46b677dba0 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -156,6 +156,7 @@ config ETH_SANDBOX_RAW config ETH_DESIGNWARE bool "Synopsys Designware Ethernet MAC" select PHYLIB + imply ETH_DESIGNWARE_SOCFPGA if ARCH_SOCFPGA help This MAC is present in SoCs from various vendors. It supports 100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to
Enable the socfpga specific designware ethernet driver by default for socfpga by implying it when enabling CONFIG_ETH_DESIGNWARE for a MACH_SOCFPGA config. This is required to remove the hacky reset and phy mode handling in arch/arm/mach-socfpga. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> --- Changes in v3: - imply CONFIG_ETH_DESIGNWARE_SOCFGPA instead of changing all defconfigs Changes in v2: - only add CONFIG_ETH_DESIGNWARE_SOCFPGA since now REGMAP and SYSCON are selected by this one drivers/net/Kconfig | 1 + 1 file changed, 1 insertion(+)