From patchwork Tue Jun 28 14:20:53 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 102391 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id D5D8DB6F5C for ; Wed, 29 Jun 2011 00:21:28 +1000 (EST) Received: (qmail 2599 invoked by alias); 28 Jun 2011 14:21:25 -0000 Received: (qmail 2571 invoked by uid 22791); 28 Jun 2011 14:21:24 -0000 X-SWARE-Spam-Status: No, hits=-2.2 required=5.0 tests=AWL, BAYES_00, FSL_HELO_NON_FQDN_1, HELO_NO_DOMAIN, TW_QE X-Spam-Check-By: sourceware.org Received: from fw-lnat.cambridge.arm.com (HELO e102483) (217.140.96.63) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 28 Jun 2011 14:20:59 +0000 Received: by e102483 (Postfix, from userid 1001) id BE7851040554; Tue, 28 Jun 2011 15:20:57 +0100 (BST) From: Ramana Radhakrishnan To: gcc-patches@gcc.gnu.org Cc: patches@linaro.org, rearnsha@arm.com, Ramana Radhakrishnan Subject: [PATCH] [ARM] Fix constraint modifiers for VFP patterns. Date: Tue, 28 Jun 2011 15:20:53 +0100 Message-Id: <1309270853-24353-1-git-send-email-ramana.radhakrishnan@linaro.org> X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, Sometime back Chung-Lin noticed that a few of the VFP patterns as below had the '+' constraint modifiers rather than the '=' constraint modifiers. I've now corrected this as follows and tested this on trunk with arm-linux-gnueabi and qemu for a v7-a neon test run. Committed. cheers Ramana 2011-06-28 Ramana Radhakrishnan * config/arm/vfp.md ("*divsf3_vfp"): Replace '+' constraint modifier with '=' constraint modifier. (*divdf3_vfp): Likewise. ("*mulsf3_vfp"): Likewise. ("*muldf3_vfp"): Likewise. ("*mulsf3negsf_vfp"): Likewise. ("*muldf3negdf_vfp"): Likewise. --- gcc/config/arm/arm.h | 2 +- gcc/config/arm/vfp.md | 13 ++++++------- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index b0d2625..edd6afd 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1597,7 +1597,7 @@ typedef struct frame. */ #define EXIT_IGNORE_STACK 1 -#define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM) +#define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) /* Determine if the epilogue should be output as RTL. You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index 42be2ff..e2165a8 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -719,7 +719,7 @@ ;; Division insns (define_insn "*divsf3_vfp" - [(set (match_operand:SF 0 "s_register_operand" "+t") + [(set (match_operand:SF 0 "s_register_operand" "=t") (div:SF (match_operand:SF 1 "s_register_operand" "t") (match_operand:SF 2 "s_register_operand" "t")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" @@ -729,7 +729,7 @@ ) (define_insn "*divdf3_vfp" - [(set (match_operand:DF 0 "s_register_operand" "+w") + [(set (match_operand:DF 0 "s_register_operand" "=w") (div:DF (match_operand:DF 1 "s_register_operand" "w") (match_operand:DF 2 "s_register_operand" "w")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" @@ -742,7 +742,7 @@ ;; Multiplication insns (define_insn "*mulsf3_vfp" - [(set (match_operand:SF 0 "s_register_operand" "+t") + [(set (match_operand:SF 0 "s_register_operand" "=t") (mult:SF (match_operand:SF 1 "s_register_operand" "t") (match_operand:SF 2 "s_register_operand" "t")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" @@ -752,7 +752,7 @@ ) (define_insn "*muldf3_vfp" - [(set (match_operand:DF 0 "s_register_operand" "+w") + [(set (match_operand:DF 0 "s_register_operand" "=w") (mult:DF (match_operand:DF 1 "s_register_operand" "w") (match_operand:DF 2 "s_register_operand" "w")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" @@ -761,9 +761,8 @@ (set_attr "type" "fmuld")] ) - (define_insn "*mulsf3negsf_vfp" - [(set (match_operand:SF 0 "s_register_operand" "+t") + [(set (match_operand:SF 0 "s_register_operand" "=t") (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t")) (match_operand:SF 2 "s_register_operand" "t")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" @@ -773,7 +772,7 @@ ) (define_insn "*muldf3negdf_vfp" - [(set (match_operand:DF 0 "s_register_operand" "+w") + [(set (match_operand:DF 0 "s_register_operand" "=w") (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w")) (match_operand:DF 2 "s_register_operand" "w")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"