[U-Boot,v2,2/3] arm: socfpga: gen5 enable designware_socfpga

Message ID 20190111194506.12051-3-simon.k.r.goldschmidt@gmail.com
State Superseded, archived
Headers show
Series
  • arm: socpfpga: gen5 clean up ETH RST & PHY mode
Related show

Commit Message

Simon Goldschmidt Jan. 11, 2019, 7:45 p.m.
Enable the socfpga specific designware ethernet driver for all Gen5
and Arria10 defconfigs.

This is required to remove the hacky reset and phy mode handling in
arch/arm/mach-socfpga.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2:
- only add CONFIG_ETH_DESIGNWARE_SOCFPGA since now REGMAP and SYSCON
  are selected by this one

 configs/socfpga_arria5_defconfig       | 1 +
 configs/socfpga_cyclone5_defconfig     | 1 +
 configs/socfpga_dbm_soc1_defconfig     | 1 +
 configs/socfpga_de0_nano_soc_defconfig | 1 +
 configs/socfpga_de10_nano_defconfig    | 1 +
 configs/socfpga_de1_soc_defconfig      | 1 +
 configs/socfpga_is1_defconfig          | 1 +
 configs/socfpga_sockit_defconfig       | 1 +
 configs/socfpga_socrates_defconfig     | 1 +
 configs/socfpga_sr1500_defconfig       | 1 +
 configs/socfpga_vining_fpga_defconfig  | 1 +
 11 files changed, 11 insertions(+)

Comments

Marek Vasut Jan. 11, 2019, 10:04 p.m. | #1
On 1/11/19 8:45 PM, Simon Goldschmidt wrote:
> Enable the socfpga specific designware ethernet driver for all Gen5
> and Arria10 defconfigs.
> 
> This is required to remove the hacky reset and phy mode handling in
> arch/arm/mach-socfpga.
> 
> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Can't the designware driver Kconfig entry just imply DESIGNWARE_SOCFPGA
if ARCH_SOCFPGA ?
Simon Goldschmidt Jan. 12, 2019, 4:01 p.m. | #2
Am 11.01.2019 um 23:04 schrieb Marek Vasut:
> On 1/11/19 8:45 PM, Simon Goldschmidt wrote:
>> Enable the socfpga specific designware ethernet driver for all Gen5
>> and Arria10 defconfigs.
>>
>> This is required to remove the hacky reset and phy mode handling in
>> arch/arm/mach-socfpga.
>>
>> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> 
> Can't the designware driver Kconfig entry just imply DESIGNWARE_SOCFPGA
> if ARCH_SOCFPGA ?

Yes it can. I just didn't know if that's acceptable. But since those two 
options are just next to each other in the Kconfig file, maybe it's ok.

Regards,
Simon
Marek Vasut Jan. 12, 2019, 6:15 p.m. | #3
On 1/12/19 5:01 PM, Simon Goldschmidt wrote:
> Am 11.01.2019 um 23:04 schrieb Marek Vasut:
>> On 1/11/19 8:45 PM, Simon Goldschmidt wrote:
>>> Enable the socfpga specific designware ethernet driver for all Gen5
>>> and Arria10 defconfigs.
>>>
>>> This is required to remove the hacky reset and phy mode handling in
>>> arch/arm/mach-socfpga.
>>>
>>> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
>>
>> Can't the designware driver Kconfig entry just imply DESIGNWARE_SOCFPGA
>> if ARCH_SOCFPGA ?
> 
> Yes it can. I just didn't know if that's acceptable. But since those two
> options are just next to each other in the Kconfig file, maybe it's ok.

Presumably it's a good idea to declutter defconfigs.

Patch

diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 0e5e74a621..a829c33dd8 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -59,6 +59,7 @@  CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index e8de0f5709..5ebc668d32 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -60,6 +60,7 @@  CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y
diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig
index b6f4f8a3dd..03a03a6ddd 100644
--- a/configs/socfpga_dbm_soc1_defconfig
+++ b/configs/socfpga_dbm_soc1_defconfig
@@ -54,6 +54,7 @@  CONFIG_MTD_DEVICE=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index 9a89bb5d68..bb202ee3c8 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -54,6 +54,7 @@  CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y
diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig
index db516891ba..3b18e302d2 100644
--- a/configs/socfpga_de10_nano_defconfig
+++ b/configs/socfpga_de10_nano_defconfig
@@ -50,6 +50,7 @@  CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y
diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig
index 5bed755723..ef3ee65760 100644
--- a/configs/socfpga_de1_soc_defconfig
+++ b/configs/socfpga_de1_soc_defconfig
@@ -49,6 +49,7 @@  CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index 682e58fdb8..9ce3ec489f 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig
@@ -54,6 +54,7 @@  CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index abbbcb94d3..39ab85547a 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -60,6 +60,7 @@  CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 53f8d3c348..29d1e557ff 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -60,6 +60,7 @@  CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index 97366cdfff..7c4bc5dfc2 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -60,6 +60,7 @@  CONFIG_PHY_MARVELL=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index 3eba09dcb1..19c2c5e1e9 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -76,6 +76,7 @@  CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_SOCFPGA=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
 CONFIG_SPI=y