From patchwork Fri Jan 11 08:22:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yash Shah X-Patchwork-Id: 1023435 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="Wa2Rv+u2"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43bbTl3r6Pz9sCX for ; Fri, 11 Jan 2019 19:23:07 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730371AbfAKIXF (ORCPT ); Fri, 11 Jan 2019 03:23:05 -0500 Received: from mail-pl1-f196.google.com ([209.85.214.196]:41650 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730347AbfAKIXF (ORCPT ); Fri, 11 Jan 2019 03:23:05 -0500 Received: by mail-pl1-f196.google.com with SMTP id u6so6449771plm.8 for ; Fri, 11 Jan 2019 00:23:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rfrxSQ6IO/YES72IRHCzaimUMiJ/XBASjBb5WLpKsYU=; b=Wa2Rv+u2eQdwyiYlbICKQpQ6NdaX1jaPNjz+94IyQ3tJ0hR3uHDkJCCsTtKzQ6GcSP Mv1GliSKAmXBM6XfDZM8Zxoxk+J5oAAf6139xX2U8xk2PDnccvIB8Lr6GygT2rhb8PqJ z8riLpZsXWNgaZHH4qalitXZ4BAZKie/qAQkazMDYdazrHXwNynT3lzYt13sl/CYYEwr KqdhDrHLKULzrb12U0tRsT0bZSh/LTx+tA96igtn+7N11RKj6471wwElpSTGeHILRJ2o mBmoCn5uNliSoiOeRsa79BDM8slG7xjswevCZDoX+XDtgkhncMDw82sXfxfAM1ae9IYZ fZCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rfrxSQ6IO/YES72IRHCzaimUMiJ/XBASjBb5WLpKsYU=; b=uczmK8uzwjBcF88TV1oFzc98LRGi1TfIwxMifv4aBIUFpfkWLT7EIvwMz3n8EVr2BZ fIeqMfBQiYgHg6XPCryX+fYMxX5DTIM/AN3rJM528rj+MvtKXdvM350mJYcg5AWfDHez Qz8wDR7leG7zWMZlZTHtSjFEP0Ck0J7GwsTsw2yZm5OGP6NGqj1M2EFFVmjgNlS+Hz6B XV7CZVEd5FGRPVq/tTsVTXbZlfWrHQf7mejrJkltkp+Meehi6cbVHBo8Xefy1bngTA4k L+q0MOn2k3xTnUpFeOa1UKAJGRBBrr4sg+EBzlYiYT/cRJz7ZS5B1K4VFz3bGy70VCJg FrHw== X-Gm-Message-State: AJcUukc1LruYmfOr0zVZEa6qyAIMJvFrJ7alE5vVRjFlYaG+2fZHzRiu i/tcKZEg2Xo0p4/lt/nkqKaPEQ== X-Google-Smtp-Source: ALg8bN72ihbGuSWy1bMDOflT2VfuMHUJbW1W9Q6keqQ5CAC8S1Uq9kyL/c6Kn2Vjow7joP31sw4nhw== X-Received: by 2002:a17:902:76cb:: with SMTP id j11mr14023595plt.179.1547194984490; Fri, 11 Jan 2019 00:23:04 -0800 (PST) Received: from buildserver-90.open-silicon.com ([114.143.65.226]) by smtp.googlemail.com with ESMTPSA id t87sm248422324pfk.122.2019.01.11.00.23.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 11 Jan 2019 00:23:03 -0800 (PST) From: Yash Shah To: palmer@sifive.com, linux-pwm@vger.kernel.org, linux-riscv@lists.infradead.org Cc: thierry.reding@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, sachin.ghadi@sifive.com, paul.walmsley@sifive.com, Yash Shah Subject: [PATCH 1/2] pwm: sifive: Add DT documentation for SiFive PWM Controller Date: Fri, 11 Jan 2019 13:52:43 +0530 Message-Id: <1547194964-16718-2-git-send-email-yash.shah@sifive.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1547194964-16718-1-git-send-email-yash.shah@sifive.com> References: <1547194964-16718-1-git-send-email-yash.shah@sifive.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org DT documentation for PWM controller added with updated compatible string. Signed-off-by: Wesley W. Terpstra [Atish: Compatible string update] Signed-off-by: Atish Patra Signed-off-by: Yash Shah --- .../devicetree/bindings/pwm/pwm-sifive.txt | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt new file mode 100644 index 0000000..e0fc22a --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt @@ -0,0 +1,37 @@ +SiFive PWM controller + +Unlike most other PWM controllers, the SiFive PWM controller currently only +supports one period for all channels in the PWM. This is set globally in DTS. +The period also has significant restrictions on the values it can achieve, +which the driver rounds to the nearest achievable frequency. + +Required properties: +- compatible: Please refer to sifive-blocks-ip-versioning.txt +- reg: physical base address and length of the controller's registers +- clocks: Should contain a clock identifier for the PWM's parent clock. +- #pwm-cells: Should be 2. + The first cell is the PWM channel number + The second cell is the PWM polarity +- sifive,approx-period-ns: the driver will get as close to this period as it can +- interrupts: one interrupt per PWM channel + +PWM RTL that corresponds to the IP block version numbers can be found +here: + +https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm + +Further information on the format of the IP +block-specific version numbers can be found in +Documentation/devicetree/bindings/sifive/sifive-blocks-ip-versioning.txt + +Examples: + +pwm: pwm@10020000 { + compatible = "sifive,fu540-c000-pwm","sifive,pwm0"; + reg = <0x0 0x10020000 0x0 0x1000>; + clocks = <&tlclk>; + interrupt-parent = <&plic>; + interrupts = <42 43 44 45>; + #pwm-cells = <2>; + sifive,approx-period-ns = <1000000>; +};