| Message ID | 20190111020849.22674-4-liq3ea@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | nvme small fix | expand |
On 1/11/19 3:08 AM, Li Qiang wrote: > There is no need to make another reference. > > Signed-off-by: Li Qiang <liq3ea@gmail.com> > Reviewed-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> > --- > hw/block/nvme.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/hw/block/nvme.c b/hw/block/nvme.c > index 0ded74fa9a..0a1da749fc 100644 > --- a/hw/block/nvme.c > +++ b/hw/block/nvme.c > @@ -1238,7 +1238,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp) > pci_conf[PCI_INTERRUPT_PIN] = 1; > pci_config_set_prog_interface(pci_dev->config, 0x2); > pci_config_set_class(pci_dev->config, PCI_CLASS_STORAGE_EXPRESS); > - pcie_endpoint_cap_init(&n->parent_obj, 0x80); > + pcie_endpoint_cap_init(pci_dev, 0x80); > > n->num_namespaces = 1; > n->reg_size = pow2ceil(0x1004 + 2 * (n->num_queues + 1) * 4); > @@ -1250,10 +1250,10 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp) > > memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, > "nvme", n->reg_size); > - pci_register_bar(&n->parent_obj, 0, > + pci_register_bar(pci_dev, 0, > PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, > &n->iomem); > - msix_init_exclusive_bar(&n->parent_obj, n->num_queues, 4, NULL); > + msix_init_exclusive_bar(pci_dev, n->num_queues, 4, NULL); > > id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID)); > id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID)); > @@ -1308,7 +1308,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp) > n->cmbuf = g_malloc0(NVME_CMBSZ_GETSIZE(n->bar.cmbsz)); > memory_region_init_io(&n->ctrl_mem, OBJECT(n), &nvme_cmb_ops, n, > "nvme-cmb", NVME_CMBSZ_GETSIZE(n->bar.cmbsz)); > - pci_register_bar(&n->parent_obj, NVME_CMBLOC_BIR(n->bar.cmbloc), > + pci_register_bar(pci_dev, NVME_CMBLOC_BIR(n->bar.cmbloc), > PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64 | > PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem); > >
diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 0ded74fa9a..0a1da749fc 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1238,7 +1238,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp) pci_conf[PCI_INTERRUPT_PIN] = 1; pci_config_set_prog_interface(pci_dev->config, 0x2); pci_config_set_class(pci_dev->config, PCI_CLASS_STORAGE_EXPRESS); - pcie_endpoint_cap_init(&n->parent_obj, 0x80); + pcie_endpoint_cap_init(pci_dev, 0x80); n->num_namespaces = 1; n->reg_size = pow2ceil(0x1004 + 2 * (n->num_queues + 1) * 4); @@ -1250,10 +1250,10 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp) memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", n->reg_size); - pci_register_bar(&n->parent_obj, 0, + pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem); - msix_init_exclusive_bar(&n->parent_obj, n->num_queues, 4, NULL); + msix_init_exclusive_bar(pci_dev, n->num_queues, 4, NULL); id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID)); id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID)); @@ -1308,7 +1308,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp) n->cmbuf = g_malloc0(NVME_CMBSZ_GETSIZE(n->bar.cmbsz)); memory_region_init_io(&n->ctrl_mem, OBJECT(n), &nvme_cmb_ops, n, "nvme-cmb", NVME_CMBSZ_GETSIZE(n->bar.cmbsz)); - pci_register_bar(&n->parent_obj, NVME_CMBLOC_BIR(n->bar.cmbloc), + pci_register_bar(pci_dev, NVME_CMBLOC_BIR(n->bar.cmbloc), PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64 | PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem);