From patchwork Fri Jan 11 00:31:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1023309 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43bP683084z9sCh for ; Fri, 11 Jan 2019 11:35:28 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id D5E1BC21D65; Fri, 11 Jan 2019 00:34:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1BC6DC22136; Fri, 11 Jan 2019 00:33:19 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1DB76C2217F; Fri, 11 Jan 2019 00:33:05 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by lists.denx.de (Postfix) with ESMTP id 309AAC22187 for ; Fri, 11 Jan 2019 00:33:02 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AEE6A1650; Thu, 10 Jan 2019 16:33:00 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C928A3F6CF; Thu, 10 Jan 2019 16:32:58 -0800 (PST) From: Andre Przywara To: Tom Rini , Simon Glass , Maxime Ripard , Jagan Teki Date: Fri, 11 Jan 2019 00:31:20 +0000 Message-Id: <20190111003121.12360-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20190111003121.12360-1-andre.przywara@arm.com> References: <20190111003121.12360-1-andre.przywara@arm.com> Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [U-Boot] [PATCH 2/3] arm: introduce _relaxed MMIO accessors X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The normal MMIO accessor macros (readX/writeX) guarantee a strong ordering, even with normal memory accesses [1]. For some MMIO operations (framebuffers being a prominent example) this is not needed, and the rather costly barrier inserted on weakly ordered systems like ARM costs some performance. To mitigate this issue, Linux introduced readX_relaxed and writeX_relaxed primitives, which only guarantee ordering between each other, so are typically faster due to the missing barrier. We probably do not care so much about performance in U-Boot, but want to have those primitives for two other reasons: - Being able to use the _relaxed macros simplifies porting drivers from Linux. - The missing barrier typically allows to generate smaller code, which can relieve some chronically tight SPL builds. Add those macros definitions by using the __raw versions of the accessors, which matches an earlier (and less complicated) version of the Linux implementation. [1] https://lwn.net/Articles/698014/ Reviewed-by: Philipp Tomsich Tested-by: Philipp Tomsich --- arch/arm/include/asm/io.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index bcbaf0d83c..5b24b88efc 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -98,11 +98,21 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; }) #define writeq(v,c) ({ u64 __v = v; __iowmb(); __arch_putq(__v,c); __v; }) +#define writeb_relaxed(v,c) __raw_writeb(v, c) +#define writew_relaxed(v,c) __raw_writew(v, c) +#define writel_relaxed(v,c) __raw_writel(v, c) +#define writeq_relaxed(v,c) __raw_writeq(v, c) + #define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; }) #define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; }) #define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; }) #define readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; }) +#define readb_relaxed(c) __raw_readb(c) +#define readw_relaxed(c) __raw_readw(c) +#define readl_relaxed(c) __raw_readl(c) +#define readq_relaxed(c) __raw_readq(c) + /* * The compiler seems to be incapable of optimising constants * properly. Spell it out to the compiler in some cases.