[V4,1/3] dt-bindings: mmc: tegra: Add pinctrl for SDMMC drive strengths

Message ID 1547160363-25323-1-git-send-email-skomatineni@nvidia.com
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  • [V4,1/3] dt-bindings: mmc: tegra: Add pinctrl for SDMMC drive strengths
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Commit Message

Sowjanya Komatineni Jan. 10, 2019, 10:46 p.m.
Add pinctrls for 3V3 and 1V8 pad drive strength configuration for
Tegra210 sdmmc.

Tegra210 sdmmc has pad configuration registers in pinmux register
domain and handled thru pinctrl to pinmux device node.

Tegra186 and Tegra194 has pad configuration register with in the
SDMMC register domain itself and are handles thru drive strength
properties in sdmmc device node.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

Comments

Adrian Hunter Jan. 14, 2019, 1:24 p.m. | #1
On 11/01/19 12:46 AM, Sowjanya Komatineni wrote:
> Program initial drive code offsets which will be used by auto
> calibration process.
> 
> Program fixed drive strengths for SDMMC pads in pad control
> register when auto cal timeouts.
> Fixed settings are based on Pre-SI analysis of the pad design.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-tegra.c | 160 ++++++++++++++++++++++++++++++-----------
>  1 file changed, 119 insertions(+), 41 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
> index e6ace31e2a41..7d681a8fa4ba 100644
> --- a/drivers/mmc/host/sdhci-tegra.c
> +++ b/drivers/mmc/host/sdhci-tegra.c
> @@ -75,6 +75,7 @@
>  #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK	0x0000000f
>  #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL	0x7
>  #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD	BIT(31)
> +#define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK		0x07FFF000
>  
>  #define SDHCI_TEGRA_AUTO_CAL_STATUS			0x1ec
>  #define SDHCI_TEGRA_AUTO_CAL_ACTIVE			BIT(31)
> @@ -121,6 +122,8 @@ struct sdhci_tegra {
>  	struct pinctrl *pinctrl_sdmmc;
>  	struct pinctrl_state *pinctrl_state_3v3;
>  	struct pinctrl_state *pinctrl_state_1v8;
> +	struct pinctrl_state *pinctrl_state_3v3_drv;
> +	struct pinctrl_state *pinctrl_state_1v8_drv;
>  
>  	struct sdhci_tegra_autocal_offsets autocal_offsets;
>  	ktime_t last_calib;
> @@ -411,6 +414,76 @@ static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host,
>  	sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
>  }
>  
> +static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage,
> +				   bool state_drvupdn)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
> +	struct sdhci_tegra_autocal_offsets *offsets =
> +						&tegra_host->autocal_offsets;
> +	struct pinctrl_state *pinctrl_drvupdn = NULL;
> +	int ret = 0;
> +	u8 drvup = 0, drvdn = 0;
> +	u32 reg;
> +
> +	if (!state_drvupdn) {
> +		/* PADS Drive Strength */
> +		if (voltage == MMC_SIGNAL_VOLTAGE_180) {
> +			if (tegra_host->pinctrl_state_1v8_drv) {
> +				pinctrl_drvupdn =
> +					tegra_host->pinctrl_state_1v8_drv;
> +			} else {
> +				drvup = offsets->pull_up_1v8_timeout;
> +				drvdn = offsets->pull_down_1v8_timeout;
> +			}
> +		} else {
> +			if (tegra_host->pinctrl_state_3v3_drv) {
> +				pinctrl_drvupdn =
> +					tegra_host->pinctrl_state_3v3_drv;
> +			} else {
> +				drvup = offsets->pull_up_3v3_timeout;
> +				drvdn = offsets->pull_down_3v3_timeout;
> +			}
> +		}
> +
> +		if (pinctrl_drvupdn != NULL) {
> +			ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
> +							pinctrl_drvupdn);
> +			if (ret < 0)
> +				dev_err(mmc_dev(host->mmc),
> +					"failed pads drvupdn, ret: %d\n", ret);
> +		} else if ((drvup) || (drvdn)) {
> +			reg = sdhci_readl(host,
> +					SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
> +			reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK;
> +			reg |= (drvup << 20) | (drvdn << 12);
> +			sdhci_writel(host, reg,
> +					SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
> +		}
> +
> +	} else {
> +		/* Dual Voltage PADS Voltage selection */
> +		if (!tegra_host->pad_control_available)
> +			return 0;
> +
> +		if (voltage == MMC_SIGNAL_VOLTAGE_180) {
> +			ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
> +						tegra_host->pinctrl_state_1v8);
> +			if (ret < 0)
> +				dev_err(mmc_dev(host->mmc),
> +					"setting 1.8V failed, ret: %d\n", ret);
> +		} else {
> +			ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
> +						tegra_host->pinctrl_state_3v3);
> +			if (ret < 0)
> +				dev_err(mmc_dev(host->mmc),
> +					"setting 3.3V failed, ret: %d\n", ret);
> +		}
> +	}
> +
> +	return ret;
> +}
> +
>  static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
>  {
>  	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> @@ -437,6 +510,7 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
>  			pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3;
>  	}
>  
> +	/* Set initial offset before auto-calibration */
>  	tegra_sdhci_set_pad_autocal_offset(host, pdpu);
>  
>  	card_clk_enabled = tegra_sdhci_configure_card_clk(host, false);
> @@ -460,19 +534,15 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
>  	if (ret) {
>  		dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n");
>  
> -		if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
> -			pdpu = offsets.pull_down_1v8_timeout << 8 |
> -			       offsets.pull_up_1v8_timeout;
> -		else
> -			pdpu = offsets.pull_down_3v3_timeout << 8 |
> -			       offsets.pull_up_3v3_timeout;
> -
> -		/* Disable automatic calibration and use fixed offsets */
> +		/* Disable automatic cal and use fixed Drive Strengths */
>  		reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
>  		reg &= ~SDHCI_AUTO_CAL_ENABLE;
>  		sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
>  
> -		tegra_sdhci_set_pad_autocal_offset(host, pdpu);
> +		ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false);
> +		if (ret < 0)
> +			dev_err(mmc_dev(host->mmc),
> +				"Setting drive strengths failed: %d\n", ret);
>  	}
>  }
>  
> @@ -511,26 +581,46 @@ static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host)
>  	err = device_property_read_u32(host->mmc->parent,
>  			"nvidia,pad-autocal-pull-up-offset-3v3-timeout",
>  			&autocal->pull_up_3v3_timeout);
> -	if (err)
> +	if (err) {
> +		if (!IS_ERR(tegra_host->pinctrl_state_3v3) &&
> +			(tegra_host->pinctrl_state_3v3_drv == NULL))
> +			pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n",
> +				mmc_hostname(host->mmc));
>  		autocal->pull_up_3v3_timeout = 0;
> +	}
>  
>  	err = device_property_read_u32(host->mmc->parent,
>  			"nvidia,pad-autocal-pull-down-offset-3v3-timeout",
>  			&autocal->pull_down_3v3_timeout);
> -	if (err)
> +	if (err) {
> +		if (!IS_ERR(tegra_host->pinctrl_state_3v3) &&
> +			(tegra_host->pinctrl_state_3v3_drv == NULL))
> +			pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n",
> +				mmc_hostname(host->mmc));
>  		autocal->pull_down_3v3_timeout = 0;
> +	}
>  
>  	err = device_property_read_u32(host->mmc->parent,
>  			"nvidia,pad-autocal-pull-up-offset-1v8-timeout",
>  			&autocal->pull_up_1v8_timeout);
> -	if (err)
> +	if (err) {
> +		if (!IS_ERR(tegra_host->pinctrl_state_1v8) &&
> +			(tegra_host->pinctrl_state_1v8_drv == NULL))
> +			pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n",
> +				mmc_hostname(host->mmc));
>  		autocal->pull_up_1v8_timeout = 0;
> +	}
>  
>  	err = device_property_read_u32(host->mmc->parent,
>  			"nvidia,pad-autocal-pull-down-offset-1v8-timeout",
>  			&autocal->pull_down_1v8_timeout);
> -	if (err)
> +	if (err) {
> +		if (!IS_ERR(tegra_host->pinctrl_state_1v8) &&
> +			(tegra_host->pinctrl_state_1v8_drv == NULL))
> +			pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n",
> +				mmc_hostname(host->mmc));
>  		autocal->pull_down_1v8_timeout = 0;
> +	}
>  
>  	err = device_property_read_u32(host->mmc->parent,
>  			"nvidia,pad-autocal-pull-up-offset-sdr104",
> @@ -743,32 +833,6 @@ static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
>  	return mmc_send_tuning(host->mmc, opcode, NULL);
>  }
>  
> -static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage)
> -{
> -	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> -	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
> -	int ret;
> -
> -	if (!tegra_host->pad_control_available)
> -		return 0;
> -
> -	if (voltage == MMC_SIGNAL_VOLTAGE_180) {
> -		ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
> -					   tegra_host->pinctrl_state_1v8);
> -		if (ret < 0)
> -			dev_err(mmc_dev(host->mmc),
> -				"setting 1.8V failed, ret: %d\n", ret);
> -	} else {
> -		ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
> -					   tegra_host->pinctrl_state_3v3);
> -		if (ret < 0)
> -			dev_err(mmc_dev(host->mmc),
> -				"setting 3.3V failed, ret: %d\n", ret);
> -	}
> -
> -	return ret;
> -}
> -
>  static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc,
>  						   struct mmc_ios *ios)
>  {
> @@ -778,7 +842,7 @@ static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc,
>  	int ret = 0;
>  
>  	if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
> -		ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage);
> +		ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true);
>  		if (ret < 0)
>  			return ret;
>  		ret = sdhci_start_signal_voltage_switch(mmc, ios);
> @@ -786,7 +850,7 @@ static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc,
>  		ret = sdhci_start_signal_voltage_switch(mmc, ios);
>  		if (ret < 0)
>  			return ret;
> -		ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage);
> +		ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true);
>  	}
>  
>  	if (tegra_host->pad_calib_required)
> @@ -805,6 +869,20 @@ static int tegra_sdhci_init_pinctrl_info(struct device *dev,
>  		return -1;
>  	}
>  
> +	tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state(
> +				tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv");
> +	if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) {
> +		if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV)
> +			tegra_host->pinctrl_state_1v8_drv = NULL;
> +	}
> +
> +	tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state(
> +				tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv");
> +	if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) {
> +		if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV)
> +			tegra_host->pinctrl_state_3v3_drv = NULL;
> +	}
> +
>  	tegra_host->pinctrl_state_3v3 =
>  		pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3");
>  	if (IS_ERR(tegra_host->pinctrl_state_3v3)) {
>
Rob Herring Jan. 15, 2019, 8:05 p.m. | #2
On Thu, 10 Jan 2019 14:46:01 -0800, Sowjanya Komatineni wrote:
> Add pinctrls for 3V3 and 1V8 pad drive strength configuration for
> Tegra210 sdmmc.
> 
> Tegra210 sdmmc has pad configuration registers in pinmux register
> domain and handled thru pinctrl to pinmux device node.
> 
> Tegra186 and Tegra194 has pad configuration register with in the
> SDMMC register domain itself and are handles thru drive strength
> properties in sdmmc device node.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
>  Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>
Ulf Hansson Jan. 22, 2019, 7:47 a.m. | #3
On Thu, 10 Jan 2019 at 23:46, Sowjanya Komatineni
<skomatineni@nvidia.com> wrote:
>
> Add pinctrls for 3V3 and 1V8 pad drive strength configuration for
> Tegra210 sdmmc.
>
> Tegra210 sdmmc has pad configuration registers in pinmux register
> domain and handled thru pinctrl to pinmux device node.
>
> Tegra186 and Tegra194 has pad configuration register with in the
> SDMMC register domain itself and are handles thru drive strength
> properties in sdmmc device node.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>

Applied for next, thanks!

Kind regards
Uffe


> ---
>  Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> index 32b4b4e41923..2cecdc71d94c 100644
> --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> @@ -39,12 +39,16 @@ sdhci@c8000200 {
>         bus-width = <8>;
>  };
>
> -Optional properties for Tegra210 and Tegra186:
> +Optional properties for Tegra210, Tegra186 and Tegra194:
>  - pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage
>    configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
>    for controllers supporting multiple voltage levels. The order of names
>    should correspond to the pin configuration states in pinctrl-0 and
>    pinctrl-1.
> +- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for
> +  Tegra210 where pad config registers are in the pinmux register domain
> +  for pull-up-strength and pull-down-strength values configuration when
> +  using pads at 3V3 and 1V8 levels.
>  - nvidia,only-1-8-v : The presence of this property indicates that the
>    controller operates at a 1.8 V fixed I/O voltage.
>  - nvidia,pad-autocal-pull-up-offset-3v3,
> --
> 2.7.4
>
Ulf Hansson Jan. 22, 2019, 7:47 a.m. | #4
On Thu, 10 Jan 2019 at 23:46, Sowjanya Komatineni
<skomatineni@nvidia.com> wrote:
>
> Add SDMMC initial pad offsets used by auto calibration process.
>
> Add SDMMC fixed drive strengths for Tegra210, Tegra186 and
> Tegra194 which are used when calibration timeouts.
>
> Fixed drive strengths are based on Pre SI Analysis of the pads.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>

For clarity, I am leaving this one for arm-soc.

Kind regards
Uffe


> ---
>  arch/arm64/boot/dts/nvidia/tegra186.dtsi |  2 ++
>  arch/arm64/boot/dts/nvidia/tegra194.dtsi | 34 +++++++++++++++++++
>  arch/arm64/boot/dts/nvidia/tegra210.dtsi | 57 ++++++++++++++++++++++++++++++--
>  3 files changed, 91 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> index 22815db4a3ed..169aee59ceac 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> @@ -315,6 +315,8 @@
>                 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
>                 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
>                 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
> +               nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
> +               nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
>                 nvidia,default-tap = <0x5>;
>                 nvidia,default-trim = <0x9>;
>                 nvidia,dqs-trim = <63>;
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index 6dfa1ca0b851..596a36705c0f 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -303,6 +303,17 @@
>                         clock-names = "sdhci";
>                         resets = <&bpmp TEGRA194_RESET_SDMMC1>;
>                         reset-names = "sdhci";
> +                       nvidia,pad-autocal-pull-up-offset-3v3-timeout =
> +                                                                       <0x07>;
> +                       nvidia,pad-autocal-pull-down-offset-3v3-timeout =
> +                                                                       <0x07>;
> +                       nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
> +                       nvidia,pad-autocal-pull-down-offset-1v8-timeout =
> +                                                                       <0x07>;
> +                       nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
> +                       nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
> +                       nvidia,default-tap = <0x9>;
> +                       nvidia,default-trim = <0x5>;
>                         status = "disabled";
>                 };
>
> @@ -314,6 +325,18 @@
>                         clock-names = "sdhci";
>                         resets = <&bpmp TEGRA194_RESET_SDMMC3>;
>                         reset-names = "sdhci";
> +                       nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
> +                       nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
> +                       nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
> +                       nvidia,pad-autocal-pull-down-offset-3v3-timeout =
> +                                                                       <0x07>;
> +                       nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
> +                       nvidia,pad-autocal-pull-down-offset-1v8-timeout =
> +                                                                       <0x07>;
> +                       nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
> +                       nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
> +                       nvidia,default-tap = <0x9>;
> +                       nvidia,default-trim = <0x5>;
>                         status = "disabled";
>                 };
>
> @@ -325,6 +348,17 @@
>                         clock-names = "sdhci";
>                         resets = <&bpmp TEGRA194_RESET_SDMMC4>;
>                         reset-names = "sdhci";
> +                       nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
> +                       nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
> +                       nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
> +                       nvidia,pad-autocal-pull-down-offset-1v8-timeout =
> +                                                                       <0x0a>;
> +                       nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
> +                       nvidia,pad-autocal-pull-down-offset-3v3-timeout =
> +                                                                       <0x0a>;
> +                       nvidia,default-tap = <0x8>;
> +                       nvidia,default-trim = <0x14>;
> +                       nvidia,dqs-trim = <40>;
>                         status = "disabled";
>                 };
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> index 2205d66b0443..41408df9d4e9 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> @@ -476,6 +476,48 @@
>                 compatible = "nvidia,tegra210-pinmux";
>                 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
>                       <0x0 0x70003000 0x0 0x294>; /* Mux registers */
> +               sdmmc1_3v3_drv: sdmmc1-3v3-drv {
> +                       sdmmc1 {
> +                               nvidia,pins = "drive_sdmmc1";
> +                               nvidia,pull-down-strength = <0x8>;
> +                               nvidia,pull-up-strength = <0x8>;
> +                       };
> +               };
> +               sdmmc1_1v8_drv: sdmmc1-1v8-drv {
> +                       sdmmc1 {
> +                               nvidia,pins = "drive_sdmmc1";
> +                               nvidia,pull-down-strength = <0x4>;
> +                               nvidia,pull-up-strength = <0x3>;
> +                       };
> +               };
> +               sdmmc2_1v8_drv: sdmmc2-1v8-drv {
> +                       sdmmc2 {
> +                               nvidia,pins = "drive_sdmmc2";
> +                               nvidia,pull-down-strength = <0x10>;
> +                               nvidia,pull-up-strength = <0x10>;
> +                       };
> +               };
> +               sdmmc3_3v3_drv: sdmmc3-3v3-drv {
> +                       sdmmc3 {
> +                               nvidia,pins = "drive_sdmmc3";
> +                               nvidia,pull-down-strength = <0x8>;
> +                               nvidia,pull-up-strength = <0x8>;
> +                       };
> +               };
> +               sdmmc3_1v8_drv: sdmmc3-1v8-drv {
> +                       sdmmc3 {
> +                               nvidia,pins = "drive_sdmmc3";
> +                               nvidia,pull-down-strength = <0x4>;
> +                               nvidia,pull-up-strength = <0x3>;
> +                       };
> +               };
> +               sdmmc4_1v8_drv: sdmmc4-1v8-drv {
> +                       sdmmc4 {
> +                               nvidia,pins = "drive_sdmmc4";
> +                               nvidia,pull-down-strength = <0x10>;
> +                               nvidia,pull-up-strength = <0x10>;
> +                       };
> +               };
>         };
>
>         /*
> @@ -1050,9 +1092,12 @@
>                 clock-names = "sdhci";
>                 resets = <&tegra_car 14>;
>                 reset-names = "sdhci";
> -               pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
> +               pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
> +                               "sdmmc-3v3-drv", "sdmmc-1v8-drv";
>                 pinctrl-0 = <&sdmmc1_3v3>;
>                 pinctrl-1 = <&sdmmc1_1v8>;
> +               pinctrl-2 = <&sdmmc1_3v3_drv>;
> +               pinctrl-3 = <&sdmmc1_1v8_drv>;
>                 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
>                 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
>                 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
> @@ -1075,6 +1120,8 @@
>                 clock-names = "sdhci";
>                 resets = <&tegra_car 9>;
>                 reset-names = "sdhci";
> +               pinctrl-names = "sdmmc-1v8-drv";
> +               pinctrl-0 = <&sdmmc2_1v8_drv>;
>                 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
>                 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
>                 nvidia,default-tap = <0x8>;
> @@ -1090,9 +1137,12 @@
>                 clock-names = "sdhci";
>                 resets = <&tegra_car 69>;
>                 reset-names = "sdhci";
> -               pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
> +               pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
> +                               "sdmmc-3v3-drv", "sdmmc-1v8-drv";
>                 pinctrl-0 = <&sdmmc3_3v3>;
>                 pinctrl-1 = <&sdmmc3_1v8>;
> +               pinctrl-2 = <&sdmmc3_3v3_drv>;
> +               pinctrl-3 = <&sdmmc3_1v8_drv>;
>                 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
>                 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
>                 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
> @@ -1110,6 +1160,9 @@
>                 clock-names = "sdhci";
>                 resets = <&tegra_car 15>;
>                 reset-names = "sdhci";
> +               pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
> +               pinctrl-0 = <&sdmmc4_1v8_drv>;
> +               pinctrl-1 = <&sdmmc4_1v8_drv>;
>                 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
>                 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
>                 nvidia,default-tap = <0x8>;
> --
> 2.7.4
>
Ulf Hansson Jan. 22, 2019, 7:47 a.m. | #5
On Thu, 10 Jan 2019 at 23:46, Sowjanya Komatineni
<skomatineni@nvidia.com> wrote:
>
> Program initial drive code offsets which will be used by auto
> calibration process.
>
> Program fixed drive strengths for SDMMC pads in pad control
> register when auto cal timeouts.
> Fixed settings are based on Pre-SI analysis of the pad design.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>

Applied for next, thanks!

Kind regards
Uffe


> ---
>  drivers/mmc/host/sdhci-tegra.c | 160 ++++++++++++++++++++++++++++++-----------
>  1 file changed, 119 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
> index e6ace31e2a41..7d681a8fa4ba 100644
> --- a/drivers/mmc/host/sdhci-tegra.c
> +++ b/drivers/mmc/host/sdhci-tegra.c
> @@ -75,6 +75,7 @@
>  #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK   0x0000000f
>  #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL    0x7
>  #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD  BIT(31)
> +#define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK         0x07FFF000
>
>  #define SDHCI_TEGRA_AUTO_CAL_STATUS                    0x1ec
>  #define SDHCI_TEGRA_AUTO_CAL_ACTIVE                    BIT(31)
> @@ -121,6 +122,8 @@ struct sdhci_tegra {
>         struct pinctrl *pinctrl_sdmmc;
>         struct pinctrl_state *pinctrl_state_3v3;
>         struct pinctrl_state *pinctrl_state_1v8;
> +       struct pinctrl_state *pinctrl_state_3v3_drv;
> +       struct pinctrl_state *pinctrl_state_1v8_drv;
>
>         struct sdhci_tegra_autocal_offsets autocal_offsets;
>         ktime_t last_calib;
> @@ -411,6 +414,76 @@ static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host,
>         sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
>  }
>
> +static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage,
> +                                  bool state_drvupdn)
> +{
> +       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +       struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
> +       struct sdhci_tegra_autocal_offsets *offsets =
> +                                               &tegra_host->autocal_offsets;
> +       struct pinctrl_state *pinctrl_drvupdn = NULL;
> +       int ret = 0;
> +       u8 drvup = 0, drvdn = 0;
> +       u32 reg;
> +
> +       if (!state_drvupdn) {
> +               /* PADS Drive Strength */
> +               if (voltage == MMC_SIGNAL_VOLTAGE_180) {
> +                       if (tegra_host->pinctrl_state_1v8_drv) {
> +                               pinctrl_drvupdn =
> +                                       tegra_host->pinctrl_state_1v8_drv;
> +                       } else {
> +                               drvup = offsets->pull_up_1v8_timeout;
> +                               drvdn = offsets->pull_down_1v8_timeout;
> +                       }
> +               } else {
> +                       if (tegra_host->pinctrl_state_3v3_drv) {
> +                               pinctrl_drvupdn =
> +                                       tegra_host->pinctrl_state_3v3_drv;
> +                       } else {
> +                               drvup = offsets->pull_up_3v3_timeout;
> +                               drvdn = offsets->pull_down_3v3_timeout;
> +                       }
> +               }
> +
> +               if (pinctrl_drvupdn != NULL) {
> +                       ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
> +                                                       pinctrl_drvupdn);
> +                       if (ret < 0)
> +                               dev_err(mmc_dev(host->mmc),
> +                                       "failed pads drvupdn, ret: %d\n", ret);
> +               } else if ((drvup) || (drvdn)) {
> +                       reg = sdhci_readl(host,
> +                                       SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
> +                       reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK;
> +                       reg |= (drvup << 20) | (drvdn << 12);
> +                       sdhci_writel(host, reg,
> +                                       SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
> +               }
> +
> +       } else {
> +               /* Dual Voltage PADS Voltage selection */
> +               if (!tegra_host->pad_control_available)
> +                       return 0;
> +
> +               if (voltage == MMC_SIGNAL_VOLTAGE_180) {
> +                       ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
> +                                               tegra_host->pinctrl_state_1v8);
> +                       if (ret < 0)
> +                               dev_err(mmc_dev(host->mmc),
> +                                       "setting 1.8V failed, ret: %d\n", ret);
> +               } else {
> +                       ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
> +                                               tegra_host->pinctrl_state_3v3);
> +                       if (ret < 0)
> +                               dev_err(mmc_dev(host->mmc),
> +                                       "setting 3.3V failed, ret: %d\n", ret);
> +               }
> +       }
> +
> +       return ret;
> +}
> +
>  static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
>  {
>         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> @@ -437,6 +510,7 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
>                         pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3;
>         }
>
> +       /* Set initial offset before auto-calibration */
>         tegra_sdhci_set_pad_autocal_offset(host, pdpu);
>
>         card_clk_enabled = tegra_sdhci_configure_card_clk(host, false);
> @@ -460,19 +534,15 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
>         if (ret) {
>                 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n");
>
> -               if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
> -                       pdpu = offsets.pull_down_1v8_timeout << 8 |
> -                              offsets.pull_up_1v8_timeout;
> -               else
> -                       pdpu = offsets.pull_down_3v3_timeout << 8 |
> -                              offsets.pull_up_3v3_timeout;
> -
> -               /* Disable automatic calibration and use fixed offsets */
> +               /* Disable automatic cal and use fixed Drive Strengths */
>                 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
>                 reg &= ~SDHCI_AUTO_CAL_ENABLE;
>                 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
>
> -               tegra_sdhci_set_pad_autocal_offset(host, pdpu);
> +               ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false);
> +               if (ret < 0)
> +                       dev_err(mmc_dev(host->mmc),
> +                               "Setting drive strengths failed: %d\n", ret);
>         }
>  }
>
> @@ -511,26 +581,46 @@ static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host)
>         err = device_property_read_u32(host->mmc->parent,
>                         "nvidia,pad-autocal-pull-up-offset-3v3-timeout",
>                         &autocal->pull_up_3v3_timeout);
> -       if (err)
> +       if (err) {
> +               if (!IS_ERR(tegra_host->pinctrl_state_3v3) &&
> +                       (tegra_host->pinctrl_state_3v3_drv == NULL))
> +                       pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n",
> +                               mmc_hostname(host->mmc));
>                 autocal->pull_up_3v3_timeout = 0;
> +       }
>
>         err = device_property_read_u32(host->mmc->parent,
>                         "nvidia,pad-autocal-pull-down-offset-3v3-timeout",
>                         &autocal->pull_down_3v3_timeout);
> -       if (err)
> +       if (err) {
> +               if (!IS_ERR(tegra_host->pinctrl_state_3v3) &&
> +                       (tegra_host->pinctrl_state_3v3_drv == NULL))
> +                       pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n",
> +                               mmc_hostname(host->mmc));
>                 autocal->pull_down_3v3_timeout = 0;
> +       }
>
>         err = device_property_read_u32(host->mmc->parent,
>                         "nvidia,pad-autocal-pull-up-offset-1v8-timeout",
>                         &autocal->pull_up_1v8_timeout);
> -       if (err)
> +       if (err) {
> +               if (!IS_ERR(tegra_host->pinctrl_state_1v8) &&
> +                       (tegra_host->pinctrl_state_1v8_drv == NULL))
> +                       pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n",
> +                               mmc_hostname(host->mmc));
>                 autocal->pull_up_1v8_timeout = 0;
> +       }
>
>         err = device_property_read_u32(host->mmc->parent,
>                         "nvidia,pad-autocal-pull-down-offset-1v8-timeout",
>                         &autocal->pull_down_1v8_timeout);
> -       if (err)
> +       if (err) {
> +               if (!IS_ERR(tegra_host->pinctrl_state_1v8) &&
> +                       (tegra_host->pinctrl_state_1v8_drv == NULL))
> +                       pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n",
> +                               mmc_hostname(host->mmc));
>                 autocal->pull_down_1v8_timeout = 0;
> +       }
>
>         err = device_property_read_u32(host->mmc->parent,
>                         "nvidia,pad-autocal-pull-up-offset-sdr104",
> @@ -743,32 +833,6 @@ static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
>         return mmc_send_tuning(host->mmc, opcode, NULL);
>  }
>
> -static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage)
> -{
> -       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> -       struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
> -       int ret;
> -
> -       if (!tegra_host->pad_control_available)
> -               return 0;
> -
> -       if (voltage == MMC_SIGNAL_VOLTAGE_180) {
> -               ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
> -                                          tegra_host->pinctrl_state_1v8);
> -               if (ret < 0)
> -                       dev_err(mmc_dev(host->mmc),
> -                               "setting 1.8V failed, ret: %d\n", ret);
> -       } else {
> -               ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
> -                                          tegra_host->pinctrl_state_3v3);
> -               if (ret < 0)
> -                       dev_err(mmc_dev(host->mmc),
> -                               "setting 3.3V failed, ret: %d\n", ret);
> -       }
> -
> -       return ret;
> -}
> -
>  static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc,
>                                                    struct mmc_ios *ios)
>  {
> @@ -778,7 +842,7 @@ static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc,
>         int ret = 0;
>
>         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
> -               ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage);
> +               ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true);
>                 if (ret < 0)
>                         return ret;
>                 ret = sdhci_start_signal_voltage_switch(mmc, ios);
> @@ -786,7 +850,7 @@ static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc,
>                 ret = sdhci_start_signal_voltage_switch(mmc, ios);
>                 if (ret < 0)
>                         return ret;
> -               ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage);
> +               ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true);
>         }
>
>         if (tegra_host->pad_calib_required)
> @@ -805,6 +869,20 @@ static int tegra_sdhci_init_pinctrl_info(struct device *dev,
>                 return -1;
>         }
>
> +       tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state(
> +                               tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv");
> +       if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) {
> +               if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV)
> +                       tegra_host->pinctrl_state_1v8_drv = NULL;
> +       }
> +
> +       tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state(
> +                               tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv");
> +       if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) {
> +               if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV)
> +                       tegra_host->pinctrl_state_3v3_drv = NULL;
> +       }
> +
>         tegra_host->pinctrl_state_3v3 =
>                 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3");
>         if (IS_ERR(tegra_host->pinctrl_state_3v3)) {
> --
> 2.7.4
>

Patch

diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
index 32b4b4e41923..2cecdc71d94c 100644
--- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
@@ -39,12 +39,16 @@  sdhci@c8000200 {
 	bus-width = <8>;
 };
 
-Optional properties for Tegra210 and Tegra186:
+Optional properties for Tegra210, Tegra186 and Tegra194:
 - pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage
   configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
   for controllers supporting multiple voltage levels. The order of names
   should correspond to the pin configuration states in pinctrl-0 and
   pinctrl-1.
+- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for
+  Tegra210 where pad config registers are in the pinmux register domain
+  for pull-up-strength and pull-down-strength values configuration when
+  using pads at 3V3 and 1V8 levels.
 - nvidia,only-1-8-v : The presence of this property indicates that the
   controller operates at a 1.8 V fixed I/O voltage.
 - nvidia,pad-autocal-pull-up-offset-3v3,