From patchwork Thu Jan 10 21:24:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 1023232 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="advQzf2g"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43bJwf127fz9sCh for ; Fri, 11 Jan 2019 08:26:58 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728740AbfAJV05 (ORCPT ); Thu, 10 Jan 2019 16:26:57 -0500 Received: from mail-lj1-f195.google.com ([209.85.208.195]:41397 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728385AbfAJV05 (ORCPT ); Thu, 10 Jan 2019 16:26:57 -0500 Received: by mail-lj1-f195.google.com with SMTP id k15-v6so11022039ljc.8 for ; Thu, 10 Jan 2019 13:26:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=lnTW1BHWZvwmVeT8D+HwSbWufOgzDNhKeATKVONbFpU=; b=advQzf2g78xGZgQqkqBkhNRseWb0pzGL+lNT0ESrUs1EJ7ZLhQCE9YAS1nJwUz0JnD UQPJ56mjpE5rr74MG4hI6PhQ67QZETcs4WSSqC2+a1PpsSqro9V/5OTXsHEMbmFwjyVC 0LAWwNIUuEYAoU/SxLGFSYKpxcuWydI/z6tzA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=lnTW1BHWZvwmVeT8D+HwSbWufOgzDNhKeATKVONbFpU=; b=ga/y0FJyb51LMz7RQ6egMsBy1orKTCwuLhG0rqhZO3m8LeloGYtHzKfxAB5/ad2aD1 MD//tKqLZJ0vJyc4JKebT2FP8+z+MwtYKdwBkXQUX73e1Wm7Y9yZXIW3T91sDgbYH8rs 1ZVQVVT3LZtsViHOBh1wRsOsUlX3+ktwU62DZaUDzCffLD78syI2EVPYBoeQLvyU/sFQ n1XwRoof8G3EC2U9cHIR5POdI4ao/9nrNtLAKAtKmo3aTYJDB3IrKu1CHib4eQYBXdyA 8zTKDH1BJQOtIQdieIcLVNZuCWkyAuJ63sYsioWExznvh6XvehmJg1gFkCRg8puPsH9h JdXg== X-Gm-Message-State: AJcUukcwl8uhPfqyS0UPNCYQs+g39bMd7IrI0REpZkOlF4XEHBMgOJl2 WGnD4QtXPcDDV1081wDdwpIUeQ== X-Google-Smtp-Source: ALg8bN5KkyCA7MpP0sRavV3RTVbYsOWFiMSBoqGX26Wv5CCECXf0znT4+mN0e7wDg+IOaNCb1ZBuOg== X-Received: by 2002:a2e:1f01:: with SMTP id f1-v6mr6862932ljf.129.1547155614820; Thu, 10 Jan 2019 13:26:54 -0800 (PST) Received: from localhost.localdomain (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id o88sm14581035lfk.38.2019.01.10.13.26.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Jan 2019 13:26:53 -0800 (PST) From: Linus Walleij To: Mark Brown , linux-spi@vger.kernel.org Cc: linux-gpio@vger.kernel.org, Bartosz Golaszewski , linuxarm@huawei.com, Linus Walleij , Janek Kotas Subject: [PATCH v2] spi: dw: Fix default polarity of native chipselect Date: Thu, 10 Jan 2019 22:24:51 +0100 Message-Id: <20190110212451.12108-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.19.2 MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The DW controller also supports platforms specifying native chipselects. When I enforce the use of high CS for drivers opting in for using GPIO descriptors, I inadvertedly switched the driver to also use active high chip select for native chip selects. As it turns out, the DW hardware driving chip selects also thinks it is weird with active low chip selects so all we need to do is remove an inversion in the driver. Cc: Janek Kotas Reported-by: Janek Kotas Fixes: 9400c41e77b8 ("spi: dw: Convert to use CS GPIO descriptors") Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Missed to alter the actually native chip select line control code. I need to be more awake. Janek can you confirm if this in combination with the previous patch solves your problem? --- drivers/spi/spi-dw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index f54b498001a9..64164f1a83f4 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -137,11 +137,10 @@ void dw_spi_set_cs(struct spi_device *spi, bool enable) struct dw_spi *dws = spi_controller_get_devdata(spi->controller); struct chip_data *chip = spi_get_ctldata(spi); - /* Chip select logic is inverted from spi_set_cs() */ if (chip && chip->cs_control) - chip->cs_control(!enable); + chip->cs_control(enable); - if (!enable) + if (enable) dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select)); else if (dws->cs_override) dw_writel(dws, DW_SPI_SER, 0);