From patchwork Thu Jan 10 19:49:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 1023196 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="g+z0Zz3g"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43bGrc3L5Yz9sCs for ; Fri, 11 Jan 2019 06:53:15 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 6F820C22102; Thu, 10 Jan 2019 19:51:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 77742C22133; Thu, 10 Jan 2019 19:50:20 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5D38FC22156; Thu, 10 Jan 2019 19:50:09 +0000 (UTC) Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by lists.denx.de (Postfix) with ESMTPS id 2B8BCC2212C for ; Thu, 10 Jan 2019 19:50:04 +0000 (UTC) Received: by mail-wm1-f67.google.com with SMTP id y8so211882wmi.4 for ; Thu, 10 Jan 2019 11:50:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=itCobqD5DgA6CbOFIa/HnB6kxPztZr3SgO7pBxbwFow=; b=g+z0Zz3gmP9uefb+qXrSj4I4bJ27cggcKL9/ipwwHYDrhqkSWBH2/+azzVeqqD4Ujx 2vAVIlC2rdPdABOUu6jjLxeMHn3oYdkEr5+AzxUxCuOLqrGUTEEtpWaJANKDs2CmX+mv uiIFJq2+SoEfB1T2jFqnShUwij3RTvbw7Onwb0T7X6jcjqLEE7cvr03I7WkcLMbiERnl fb9EnUsAgJcxC9rn8KAJgyaUCsQ5SrpI8DAuyRQupxul36n+tAmmZXgdiwHekHv5JIqd /Jo7xZnaqfk21yn7+BON8ZtTUaRz2n2Z/Y0Xp0Q57iRK9wU9PXwDevzCYlqKg30kEKfw l1rA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=itCobqD5DgA6CbOFIa/HnB6kxPztZr3SgO7pBxbwFow=; b=U7WJBX5jjZj/G0lYJ60GsHchD0tYyRjG/45BAr5A0gWqrO3eZfa6yRwmtCybJmvZpZ sAwme/92ZqzFOtNo6re/ICgGEx0YdbO5og3OE/SIciiXmNyqpHYcXxJb58PQO2mfdmOL xXGIAC2A5AmmjdA/I3mL3fCSuBTk+2hBvPykibCDfrr8BJJH7oWYGFgi73yEdf67WQZ6 oiJWCAFjoxZjKGlDoICqiBTWCyzgAmbZt3YGM+Qb9ie/4zFSYozuAaJE1HHLW3WffG8P ho/s+qtqsCnCEUEQJKK1XEK1xS8FOlDz41WGEElDwSsaKJctgkQzvZgXfjoHxko3MbmL D12Q== X-Gm-Message-State: AJcUukcFRJ4K0chou3Cr80+6AEWDtKvLEb+yNk/32yo9dAe4O6nqMjIG 2fQzeYQQRWlmJtzSMgjeQ/Y= X-Google-Smtp-Source: ALg8bN6ZAnhS14kU3qQqLMRZCJdkgDgy0bFs/b8TWbbNQxX4O0JeYdJgB8d2SmKgLciBCt+nm1mU5w== X-Received: by 2002:a1c:e1d5:: with SMTP id y204mr141635wmg.65.1547149803651; Thu, 10 Jan 2019 11:50:03 -0800 (PST) Received: from ubuntu.home ([2a02:8071:6a3:700:8c22:ee0c:efc8:ed86]) by smtp.gmail.com with ESMTPSA id a187sm17881800wmf.33.2019.01.10.11.50.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 10 Jan 2019 11:50:02 -0800 (PST) From: Simon Goldschmidt To: Marek Vasut , u-boot@lists.denx.de Date: Thu, 10 Jan 2019 20:49:53 +0100 Message-Id: <20190110194954.23950-3-simon.k.r.goldschmidt@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190110194954.23950-1-simon.k.r.goldschmidt@gmail.com> References: <20190110194954.23950-1-simon.k.r.goldschmidt@gmail.com> Cc: Tom Rini , Stefan Roese , Pavel Machek , Chin-Liang See Subject: [U-Boot] [PATCH 2/3] arm: socfpga: gen5 enable designware_socfpga X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Enable the socfpga specific designeware ethernet driver for all Gen5 and Arria10 defconfigs. To make it work, enable REGMAP and SYSCON, too. This is required to remove the hacky reset and phy mode handling in arch/arm/mach-socfpga. Signed-off-by: Simon Goldschmidt --- configs/socfpga_arria5_defconfig | 3 +++ configs/socfpga_cyclone5_defconfig | 3 +++ configs/socfpga_dbm_soc1_defconfig | 3 +++ configs/socfpga_de0_nano_soc_defconfig | 3 +++ configs/socfpga_de10_nano_defconfig | 3 +++ configs/socfpga_de1_soc_defconfig | 3 +++ configs/socfpga_is1_defconfig | 3 +++ configs/socfpga_sockit_defconfig | 3 +++ configs/socfpga_socrates_defconfig | 3 +++ configs/socfpga_sr1500_defconfig | 3 +++ configs/socfpga_vining_fpga_defconfig | 3 +++ 11 files changed, 33 insertions(+) diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 0e5e74a621..15cc16b111 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -41,6 +41,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk" CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y @@ -59,6 +61,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index e8de0f5709..2a432d2007 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -41,6 +41,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk" CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y @@ -60,6 +62,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig index b6f4f8a3dd..e7726dc3cc 100644 --- a/configs/socfpga_dbm_soc1_defconfig +++ b/configs/socfpga_dbm_soc1_defconfig @@ -42,6 +42,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_dbm_soc1" CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y @@ -54,6 +56,7 @@ CONFIG_MTD_DEVICE=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 9a89bb5d68..33a412d340 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -41,6 +41,8 @@ CONFIG_CMD_UBI=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc" CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y @@ -54,6 +56,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index db516891ba..662e895af2 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -37,6 +37,8 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_nano" CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y @@ -50,6 +52,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index 5bed755723..d02bf1c6cf 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -37,6 +37,8 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc" CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y @@ -49,6 +51,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index 682e58fdb8..97125efae4 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -38,6 +38,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8 CONFIG_FPGA_SOCFPGA=y @@ -54,6 +56,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index abbbcb94d3..a1019d12fc 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -41,6 +41,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit" CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y @@ -60,6 +62,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 53f8d3c348..4ffce80793 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -42,6 +42,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y @@ -60,6 +62,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 97366cdfff..d4720e5580 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -42,6 +42,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8 CONFIG_FPGA_SOCFPGA=y @@ -60,6 +62,7 @@ CONFIG_PHY_MARVELL=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 3eba09dcb1..c3d4b815f1 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -47,6 +47,8 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y @@ -76,6 +78,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y