From patchwork Mon Jun 27 17:46:56 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Mason X-Patchwork-Id: 102240 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id C77A5B6F67 for ; Tue, 28 Jun 2011 03:49:27 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752911Ab1F0Rs6 (ORCPT ); Mon, 27 Jun 2011 13:48:58 -0400 Received: from mail-pz0-f46.google.com ([209.85.210.46]:53528 "EHLO mail-pz0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752875Ab1F0RrB (ORCPT ); Mon, 27 Jun 2011 13:47:01 -0400 Received: by pzk9 with SMTP id 9so3105124pzk.19 for ; Mon, 27 Jun 2011 10:47:00 -0700 (PDT) Received: by 10.68.17.229 with SMTP id r5mr1942828pbd.356.1309196820645; Mon, 27 Jun 2011 10:47:00 -0700 (PDT) Received: from scylla (cpe-70-113-48-102.austin.res.rr.com [70.113.48.102]) by mx.google.com with ESMTPS id u6sm4456558pbh.64.2011.06.27.10.46.57 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 27 Jun 2011 10:46:59 -0700 (PDT) Received: by scylla (sSMTP sendmail emulation); Mon, 27 Jun 2011 12:46:56 -0500 From: Jon Mason To: Stephen Hemminger Cc: netdev@vger.kernel.org Subject: [PATCH 14/19] sky2: remove unnecessary reads of PCI_CAP_ID_EXP Date: Mon, 27 Jun 2011 12:46:56 -0500 Message-Id: <1309196816-16198-1-git-send-email-jdmason@kudzu.us> X-Mailer: git-send-email 1.7.5.4 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The PCIE capability offset is saved during PCI bus walking. It will remove an unnecessary search in the PCI configuration space if this value is referenced instead of reacquiring it. Also, pci_is_pcie is a better way of determining if the device is PCIE or not (as it uses the same saved PCIE capability offset). Signed-off-by: Jon Mason Acked-by: Stephen Hemminger --- drivers/net/sky2.c | 15 +++++++-------- 1 files changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c index d252cb1..e14b86e 100644 --- a/drivers/net/sky2.c +++ b/drivers/net/sky2.c @@ -1449,7 +1449,7 @@ static void sky2_rx_start(struct sky2_port *sky2) sky2_qset(hw, rxq); /* On PCI express lowering the watermark gives better performance */ - if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) + if (pci_is_pcie(hw->pdev)) sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); /* These chips have no ram buffer? @@ -3072,7 +3072,7 @@ static void sky2_reset(struct sky2_hw *hw) { struct pci_dev *pdev = hw->pdev; u16 status; - int i, cap; + int i; u32 hwe_mask = Y2_HWE_ALL_MASK; /* disable ASF */ @@ -3108,8 +3108,7 @@ static void sky2_reset(struct sky2_hw *hw) sky2_write8(hw, B0_CTST, CS_MRST_CLR); - cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); - if (cap) { + if (pci_is_pcie(pdev)) { sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, 0xfffffffful); @@ -3171,11 +3170,11 @@ static void sky2_reset(struct sky2_hw *hw) /* check if PSMv2 was running before */ reg = sky2_pci_read16(hw, PSM_CONFIG_REG3); - if (reg & PCI_EXP_LNKCTL_ASPMC) { - cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); + if (reg & PCI_EXP_LNKCTL_ASPMC) /* restore the PCIe Link Control register */ - sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg); - } + sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL, + reg); + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */