[1/2] dt-bindings: imx: Add pinctrl binding doc for imx8mm

Message ID 1546938582-23377-1-git-send-email-ping.bai@nxp.com
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  • [1/2] dt-bindings: imx: Add pinctrl binding doc for imx8mm
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robh/checkpatch warning "total: 614 errors, 615 warnings, 665 lines checked"

Commit Message

Jacky Bai Jan. 8, 2019, 9:05 a.m.
Add binding doc imx8mm pinctrl driver.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
---
 .../bindings/pinctrl/fsl,imx8mm-pinctrl.txt        |  36 ++
 include/dt-bindings/pinctrl/imx8mm-pinfunc.h       | 629 +++++++++++++++++++++
 2 files changed, 665 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt
 create mode 100644 include/dt-bindings/pinctrl/imx8mm-pinfunc.h

Comments

Aisheng Dong Jan. 11, 2019, 12:25 p.m. | #1
> From: Jacky Bai
> Sent: Tuesday, January 8, 2019 5:05 PM
> Subject: [PATCH 1/2] dt-bindings: imx: Add pinctrl binding doc for imx8mm
> 
> Add binding doc imx8mm pinctrl driver.
> 
> Signed-off-by: Bai Ping <ping.bai@nxp.com>
> ---
>  .../bindings/pinctrl/fsl,imx8mm-pinctrl.txt        |  36 ++
>  include/dt-bindings/pinctrl/imx8mm-pinfunc.h       | 629
> +++++++++++++++++++++
>  2 files changed, 665 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt
>  create mode 100644 include/dt-bindings/pinctrl/imx8mm-pinfunc.h
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt
> b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt
> new file mode 100644
> index 0000000..524a16f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt
> @@ -0,0 +1,36 @@
> +* Freescale IMX8MM IOMUX Controller
> +
> +Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
> +for common binding part and usage.
> +
> +Required properties:
> +- compatible: "fsl,imx8mm-iomuxc"
> +- reg: should contain the base physical address and size of the iomuxc
> +  registers.
> +
> +Required properties in sub-nodes:
> +- fsl,pins: each entry consists of 6 integers and represents the mux and config
> +  setting for one pin.  The first 5 integers <mux_reg conf_reg input_reg
> mux_val
> +  input_val> are specified using a PIN_FUNC_ID macro, which can be found
> in
> +  <dt-bindings/pinctrl/imx8mm-pinfunc.h>. The last integer CONFIG is
> +  the pad setting value like pull-up on this pin.  Please refer to i.MX8M Mini
> +  Reference Manual for detailed CONFIG settings.
> +
> +Examples:
> +
> +&uart1 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_uart1>;
> +};
> +
> +iomuxc: pinctrl@30330000 {
> +        compatible = "fsl,imx8mm-iomuxc";
> +        reg = <0x0 0x30330000 0x0 0x10000>;
> +
> +        pinctrl_uart1: uart1grp {
> +                fsl,pins = <
> +                        MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX
> 0x140
> +                        MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX
> 0x140
> +                >;
> +        };
> +};
> diff --git a/include/dt-bindings/pinctrl/imx8mm-pinfunc.h
> b/include/dt-bindings/pinctrl/imx8mm-pinfunc.h
> new file mode 100644
> index 0000000..e25f7fc
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/imx8mm-pinfunc.h

As suggested by Shawn before, if the headfile is not used by others,
we'd better to keep it under arch/arm/boot/dts like other imx SoCs.

Otherwise, the patch looks good to me.
You can resend with my Ack.

Regards
Dong Aisheng

> @@ -0,0 +1,629 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2017-2018 NXP
> + */
> +
> +#ifndef __DTS_IMX8MM_PINFUNC_H
> +#define __DTS_IMX8MM_PINFUNC_H
> +
> +/*
> + * The pin function ID is a tuple of
> + * <mux_reg conf_reg input_reg mux_mode input_val>
> + */
> +
> +#define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0
> 0x028 0x290 0x000 0x0 0x0
> +#define
> MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT
> 0x028 0x290 0x4C0 0x1 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K
> 0x028 0x290 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1
> 0x028 0x290 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL
> 0x028 0x290 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1
> 0x02C 0x294 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT
> 0x02C 0x294 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M
> 0x02C 0x294 0x4BC 0x5 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2
> 0x02C 0x294 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE
> 0x02C 0x294 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2
> 0x030 0x298 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B
> 0x030 0x298 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY
> 0x030 0x298 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO02_SJC_DE_B
> 0x030 0x298 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3
> 0x034 0x29C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT
> 0x034 0x29C 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0
> 0x034 0x29C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK
> 0x034 0x29C 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO03_SJC_DONE
> 0x034 0x29C 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4
> 0x038 0x2A0 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT
> 0x038 0x2A0 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1
> 0x038 0x2A0 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV
> 0x038 0x2A0 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG
> 0x038 0x2A0 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5
> 0x03C 0x2A4 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO05_M4_NMI
> 0x03C 0x2A4 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY
> 0x03C 0x2A4 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT
> 0x03C 0x2A4 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG
> 0x03C 0x2A4 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6
> 0x040 0x2A8 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO06_ENET1_MDC
> 0x040 0x2A8 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO06_USDHC1_CD_B
> 0x040 0x2A8 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3
> 0x040 0x2A8 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG
> 0x040 0x2A8 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7
> 0x044 0x2AC 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO07_ENET1_MDIO
> 0x044 0x2AC 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO07_USDHC1_WP
> 0x044 0x2AC 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4
> 0x044 0x2AC 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG
> 0x044 0x2AC 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8
> 0x048 0x2B0 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN
> 0x048 0x2B0 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO08_USDHC2_RESET_B
> 0x048 0x2B0 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT
> 0x048 0x2B0 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG
> 0x048 0x2B0 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9
> 0x04C 0x2B4 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT
> 0x04C 0x2B4 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0
> 0x04C 0x2B4 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP
> 0x04C 0x2B4 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG
> 0x04C 0x2B4 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10
> 0x050 0x2B8 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO10_USB1_OTG_ID
> 0x050 0x2B8 0x000 0x1 0x0
> +#define
> MX8MM_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED
> 0x050 0x2B8 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11
> 0x054 0x2BC 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO11_USB2_OTG_ID
> 0x054 0x2BC 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY
> 0x054 0x2BC 0x4BC 0x5 0x1
> +#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0
> 0x054 0x2BC 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS
> 0x054 0x2BC 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12
> 0x058 0x2C0 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR
> 0x058 0x2C0 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1
> 0x058 0x2C0 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1
> 0x058 0x2C0 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0
> 0x058 0x2C0 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13
> 0x05C 0x2C4 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC
> 0x05C 0x2C4 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT
> 0x05C 0x2C4 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2
> 0x05C 0x2C4 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1
> 0x05C 0x2C4 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14
> 0x060 0x2C8 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR
> 0x060 0x2C8 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT
> 0x060 0x2C8 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1
> 0x060 0x2C8 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2
> 0x060 0x2C8 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15
> 0x064 0x2CC 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC
> 0x064 0x2CC 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT
> 0x064 0x2CC 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2
> 0x064 0x2CC 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB
> 0x064 0x2CC 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_ENET_MDC_ENET1_MDC
> 0x068 0x2D0 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16
> 0x068 0x2D0 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO
> 0x06C 0x2D4 0x4C0 0x0 0x1
> +#define MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17
> 0x06C 0x2D4 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3
> 0x070 0x2D8 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18
> 0x070 0x2D8 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2
> 0x074 0x2DC 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK
> 0x074 0x2DC 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19
> 0x074 0x2DC 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1
> 0x078 0x2E0 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20
> 0x078 0x2E0 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0
> 0x07C 0x2E4 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21
> 0x07C 0x2E4 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL
> 0x080 0x2E8 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22
> 0x080 0x2E8 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC
> 0x084 0x2EC 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ENET_TXC_ENET1_TX_ER
> 0x084 0x2EC 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23
> 0x084 0x2EC 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL
> 0x088 0x2F0 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24
> 0x088 0x2F0 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC
> 0x08C 0x2F4 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER
> 0x08C 0x2F4 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25
> 0x08C 0x2F4 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0
> 0x090 0x2F8 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26
> 0x090 0x2F8 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1
> 0x094 0x2FC 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27
> 0x094 0x2FC 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2
> 0x098 0x300 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28
> 0x098 0x300 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3
> 0x09C 0x304 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29
> 0x09C 0x304 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
> 0x0A0 0x308 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0
> 0x0A0 0x308 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
> 0x0A4 0x30C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1
> 0x0A4 0x30C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
> 0x0A8 0x310 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2
> 0x0A8 0x31  0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
> 0x0AC 0x314 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3
> 0x0AC 0x314 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
> 0x0B0 0x318 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4
> 0x0B0 0x318 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
> 0x0B4 0x31C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5
> 0x0B4 0x31C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4
> 0x0B8 0x320 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6
> 0x0B8 0x320 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5
> 0x0BC 0x324 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7
> 0x0BC 0x324 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6
> 0x0C0 0x328 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8
> 0x0C0 0x328 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7
> 0x0C4 0x32C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9
> 0x0C4 0x32C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B
> 0x0C8 0x330 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10
> 0x0C8 0x330 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE
> 0x0CC 0x334 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11
> 0x0CC 0x334 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B
> 0x0D0 0x338 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12
> 0x0D0 0x338 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK
> 0x0D4 0x33C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD2_CLK_GPIO2_IO13
> 0x0D4 0x33C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0
> 0x0D4 0x33C 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0
> 0x0D4 0x33C 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD
> 0x0D8 0x340 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD2_CMD_GPIO2_IO14
> 0x0D8 0x340 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1
> 0x0D8 0x340 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1
> 0x0D8 0x340 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0
> 0x0DC 0x344 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD2_DATA0_GPIO2_IO15
> 0x0DC 0x344 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2
> 0x0DC 0x344 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2
> 0x0DC 0x344 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1
> 0x0E0 0x348 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD2_DATA1_GPIO2_IO16
> 0x0E0 0x348 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT
> 0x0E0 0x348 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3
> 0x0E0 0x348 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2
> 0x0E4 0x34C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD2_DATA2_GPIO2_IO17
> 0x0E4 0x34C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP
> 0x0E4 0x34C 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4
> 0x0E4 0x34C 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3
> 0x0E8 0x350 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD2_DATA3_GPIO2_IO18
> 0x0E8 0x350 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET
> 0x0E8 0x350 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B
> 0x0EC 0x354 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19
> 0x0EC 0x354 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET
> 0x0EC 0x354 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SD2_WP_USDHC2_WP
> 0x0F0 0x358 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SD2_WP_GPIO2_IO20
> 0x0F0 0x358 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SD2_WP_SIM_M_HMASTLOCK
> 0x0F0 0x358 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE
> 0x0F4 0x35C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK
> 0x0F4 0x35C 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0
> 0x0F4 0x35C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_NAND_ALE_SIM_M_HPROT0
> 0x0F4 0x35C 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B
> 0x0F8 0x360 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B
> 0x0F8 0x360 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1
> 0x0F8 0x360 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_NAND_CE0_B_SIM_M_HPROT1
> 0x0F8 0x360 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B
> 0x0FC 0x364 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B
> 0x0FC 0x364 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE
> 0x0FC 0x364 0x000 0x2 0x0
> +#define MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2
> 0x0FC 0x364 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_NAND_CE1_B_SIM_M_HPROT2
> 0x0FC 0x364 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B
> 0x100 0x368 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B
> 0x100 0x368 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5
> 0x100 0x368 0x000 0x2 0x0
> +#define MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3
> 0x100 0x368 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_NAND_CE2_B_SIM_M_HPROT3
> 0x100 0x368 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B
> 0x104 0x36C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B
> 0x104 0x36C 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6
> 0x104 0x36C 0x000 0x2 0x0
> +#define MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4
> 0x104 0x36C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_NAND_CE3_B_SIM_M_HADDR0
> 0x104 0x36C 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE
> 0x108 0x370 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK
> 0x108 0x370 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7
> 0x108 0x370 0x000 0x2 0x0
> +#define MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5
> 0x108 0x370 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_NAND_CLE_SIM_M_HADDR1
> 0x108 0x370 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00
> 0x10C 0x374 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0
> 0x10C 0x374 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6
> 0x10C 0x374 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_NAND_DATA00_SIM_M_HADDR2
> 0x10C 0x374 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01
> 0x110 0x378 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1
> 0x110 0x378 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7
> 0x110 0x378 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_NAND_DATA01_SIM_M_HADDR3
> 0x110 0x378 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02
> 0x114 0x37C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2
> 0x114 0x37C 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8
> 0x114 0x37C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_NAND_DATA02_SIM_M_HADDR4
> 0x114 0x37C 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03
> 0x118 0x380 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3
> 0x118 0x380 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9
> 0x118 0x380 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_NAND_DATA03_SIM_M_HADDR5
> 0x118 0x380 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04
> 0x11C 0x384 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0
> 0x11C 0x384 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0
> 0x11C 0x384 0x000 0x2 0x0
> +#define MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10
> 0x11C 0x384 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_NAND_DATA04_SIM_M_HADDR6
> 0x11C 0x384 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05
> 0x120 0x388 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1
> 0x120 0x388 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1
> 0x120 0x388 0x000 0x2 0x0
> +#define MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11
> 0x120 0x388 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_NAND_DATA05_SIM_M_HADDR7
> 0x120 0x388 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06
> 0x124 0x38C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2
> 0x124 0x38C 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2
> 0x124 0x38C 0x000 0x2 0x0
> +#define MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12
> 0x124 0x38C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_NAND_DATA06_SIM_M_HADDR8
> 0x124 0x38C 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07
> 0x128 0x390 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3
> 0x128 0x390 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3
> 0x128 0x390 0x000 0x2 0x0
> +#define MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13
> 0x128 0x390 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_NAND_DATA07_SIM_M_HADDR9
> 0x128 0x390 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_NAND_DQS_RAWNAND_DQS
> 0x12C 0x394 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS
> 0x12C 0x394 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14
> 0x12C 0x394 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_NAND_DQS_SIM_M_HADDR10
> 0x12C 0x394 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B
> 0x130 0x398 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_NAND_RE_B_QSPI_B_DQS
> 0x130 0x398 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4
> 0x130 0x398 0x000 0x2 0x0
> +#define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15
> 0x130 0x398 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11
> 0x130 0x398 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B
> 0x134 0x39C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16
> 0x134 0x39C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12
> 0x134 0x39C 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B
> 0x138 0x3A0 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK
> 0x138 0x3A0 0x000 0x12 0x0
> +#define MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17
> 0x138 0x3A0 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_NAND_WE_B_SIM_M_HADDR13
> 0x138 0x3A0 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B
> 0x13C 0x3A4 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD
> 0x13C 0x3A4 0x000 0x2 0x0
> +#define MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18
> 0x13C 0x3A4 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_NAND_WP_B_SIM_M_HADDR14
> 0x13C 0x3A4 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC
> 0x140 0x3A8 0x4E4 0x0 0x0
> +#define MX8MM_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0
> 0x140 0x3A8 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19
> 0x140 0x3A8 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK
> 0x144 0x3AC 0x4D0 0x0 0x0
> +#define MX8MM_IOMUXC_SAI5_RXC_SAI1_TX_DATA1
> 0x144 0x3AC 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI5_RXC_PDM_CLK
> 0x144 0x3AC 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20
> 0x144 0x3AC 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0
> 0x148 0x3B0 0x4D4 0x0 0x0
> +#define MX8MM_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2
> 0x148 0x3B0 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0
> 0x148 0x3B0 0x534 0x4 0x0
> +#define MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21
> 0x148 0x3B0 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1
> 0x14C 0x3B4 0x4D8 0x0 0x0
> +#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3
> 0x14C 0x3B4 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC
> 0x14C 0x3B4 0x4CC 0x2 0x0
> +#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC
> 0x14C 0x3B4 0x4EC 0x3 0x0
> +#define MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1
> 0x14C 0x3B4 0x538 0x4 0x0
> +#define MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22
> 0x14C 0x3B4 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2
> 0x150 0x3B8 0x4DC 0x0 0x0
> +#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4
> 0x150 0x3B8 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC
> 0x150 0x3B8 0x4CC 0x2 0x1
> +#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK
> 0x150 0x3B8 0x4E8 0x3 0x0
> +#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2
> 0x150 0x3B8 0x53c 0x4 0x0
> +#define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23
> 0x150 0x3B8 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3
> 0x154 0x3BC 0x4E0 0x0 0x0
> +#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5
> 0x154 0x3BC 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC
> 0x154 0x3BC 0x4CC 0x2 0x2
> +#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0
> 0x154 0x3BC 0x000 0x3 0x0
> +#define MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3
> 0x154 0x3BC 0x540 0x4 0x0
> +#define MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24
> 0x154 0x3BC 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK
> 0x158 0x3C0 0x52C 0x0 0x0
> +#define MX8MM_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK
> 0x158 0x3C0 0x4C8 0x1 0x0
> +#define MX8MM_IOMUXC_SAI5_MCLK_SAI4_MCLK
> 0x158 0x3C0 0x000 0x2 0x0
> +#define MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25
> 0x158 0x3C0 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK
> 0x158 0x3C0 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC
> 0x15C 0x3C4 0x4C4 0x0 0x0
> +#define MX8MM_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC
> 0x15C 0x3C4 0x4E4 0x1 0x1
> +#define MX8MM_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK
> 0x15C 0x3C4 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0
> 0x15C 0x3C4 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_RXFS_SIM_M_HADDR15
> 0x15C 0x3C4 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK
> 0x160 0x3C8 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI1_RXC_SAI5_RX_BCLK
> 0x160 0x3C8 0x4D0 0x1 0x1
> +#define MX8MM_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL
> 0x160 0x3C8 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1
> 0x160 0x3C8 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_RXC_SIM_M_HADDR16
> 0x160 0x3C8 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0
> 0x164 0x3CC 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0
> 0x164 0x3CC 0x4D4 0x1 0x1
> +#define MX8MM_IOMUXC_SAI1_RXD0_PDM_DATA0
> 0x164 0x3CC 0x534 0x3 0x1
> +#define MX8MM_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0
> 0x164 0x3CC 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2
> 0x164 0x3CC 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0
> 0x164 0x3CC 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD0_SIM_M_HADDR17
> 0x164 0x3CC 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1
> 0x168 0x3D0 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1
> 0x168 0x3D0 0x4D8 0x1 0x1
> +#define MX8MM_IOMUXC_SAI1_RXD1_PDM_DATA1
> 0x168 0x3D0 0x538 0x3 0x1
> +#define MX8MM_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1
> 0x168 0x3D0 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3
> 0x168 0x3D0 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1
> 0x168 0x3D0 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD1_SIM_M_HADDR18
> 0x168 0x3D0 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2
> 0x16C 0x3D4 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2
> 0x16C 0x3D4 0x4DC 0x1 0x1
> +#define MX8MM_IOMUXC_SAI1_RXD2_PDM_DATA2
> 0x16C 0x3D4 0x53C 0x3 0x1
> +#define MX8MM_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2
> 0x16C 0x3D4 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4
> 0x16C 0x3D4 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2
> 0x16C 0x3D4 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD2_SIM_M_HADDR19
> 0x16C 0x3D4 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3
> 0x170 0x3D8 0x4E0 0x0 0x1
> +#define MX8MM_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3
> 0x170 0x3D8 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD3_PDM_DATA3
> 0x170 0x3D8 0x540 0x3 0x1
> +#define MX8MM_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3
> 0x170 0x3D8 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5
> 0x170 0x3D8 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3
> 0x170 0x3D8 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD3_SIM_M_HADDR20
> 0x170 0x3D8 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4
> 0x174 0x3DC 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK
> 0x174 0x3DC 0x51C 0x1 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK
> 0x174 0x3DC 0x510 0x2 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4
> 0x174 0x3DC 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6
> 0x174 0x3DC 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4
> 0x174 0x3DC 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD4_SIM_M_HADDR21
> 0x174 0x3DC 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5
> 0x178 0x3E0 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0
> 0x178 0x3E0 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0
> 0x178 0x3E0 0x514 0x2 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC
> 0x178 0x3E0 0x4C4 0x3 0x1
> +#define MX8MM_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5
> 0x178 0x3E0 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7
> 0x178 0x3E0 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5
> 0x178 0x3E0 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD5_SIM_M_HADDR22
> 0x178 0x3E0 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6
> 0x17C 0x3E4 0x520 0x0 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC
> 0x17C 0x3E4 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC
> 0x17C 0x3E4 0x518 0x2 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6
> 0x17C 0x3E4 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8
> 0x17C 0x3E4 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6
> 0x17C 0x3E4 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD6_SIM_M_HADDR23
> 0x17C 0x3E4 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7
> 0x180 0x3E8 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD7_SAI6_MCLK
> 0x180 0x3E8 0x530 0x1 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC
> 0x180 0x3E8 0x4CC 0x2 0x4
> +#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4
> 0x180 0x3E8 0x000 0x3 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7
> 0x180 0x3E8 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9
> 0x180 0x3E8 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7
> 0x180 0x3E8 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SAI1_RXD7_SIM_M_HADDR24
> 0x180 0x3E8 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC
> 0x184 0x3EC 0x4CC 0x0 0x3
> +#define MX8MM_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC
> 0x184 0x3EC 0x4EC 0x1 0x1
> +#define MX8MM_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO
> 0x184 0x3EC 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10
> 0x184 0x3EC 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_TXFS_SIM_M_HADDR25
> 0x184 0x3EC 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK
> 0x188 0x3F0 0x4C8 0x0 0x1
> +#define MX8MM_IOMUXC_SAI1_TXC_SAI5_TX_BCLK
> 0x188 0x3F0 0x4E8 0x1 0x1
> +#define MX8MM_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI
> 0x188 0x3F0 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11
> 0x188 0x3F0 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_TXC_SIM_M_HADDR26
> 0x188 0x3F0 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0
> 0x18C 0x3F4 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0
> 0x18C 0x3F4 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8
> 0x18C 0x3F4 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12
> 0x18C 0x3F4 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8
> 0x18C 0x3F4 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD0_SIM_M_HADDR27
> 0x18C 0x3F4 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1
> 0x190 0x3F8 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1
> 0x190 0x3F8 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9
> 0x190 0x3F8 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13
> 0x190 0x3F8 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9
> 0x190 0x3F8 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD1_SIM_M_HADDR28
> 0x190 0x3F8 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2
> 0x194 0x3FC 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2
> 0x194 0x3FC 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10
> 0x194 0x3FC 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14
> 0x194 0x3FC 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10
> 0x194 0x3FC 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD2_SIM_M_HADDR29
> 0x194 0x3FC 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3
> 0x198 0x400 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3
> 0x198 0x400 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11
> 0x198 0x400 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15
> 0x198 0x400 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11
> 0x198 0x400 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD3_SIM_M_HADDR30
> 0x198 0x400 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4
> 0x19C 0x404 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK
> 0x19C 0x404 0x510 0x1 0x1
> +#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK
> 0x19C 0x404 0x51C 0x2 0x1
> +#define MX8MM_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12
> 0x19C 0x404 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16
> 0x19C 0x404 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12
> 0x19C 0x404 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD4_SIM_M_HADDR31
> 0x19C 0x404 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5
> 0x1A0 0x408 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0
> 0x1A0 0x408 0x514 0x1 0x1
> +#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0
> 0x1A0 0x408 0x000 0x2 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13
> 0x1A0 0x408 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17
> 0x1A0 0x408 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13
> 0x1A0 0x408 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD5_SIM_M_HBURST0
> 0x1A0 0x408 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6
> 0x1A4 0x40C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC
> 0x1A4 0x40C 0x518 0x1 0x1
> +#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC
> 0x1A4 0x40C 0x520 0x2 0x1
> +#define MX8MM_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14
> 0x1A4 0x40C 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18
> 0x1A4 0x40C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14
> 0x1A4 0x40C 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD6_SIM_M_HBURST1
> 0x1A4 0x40C 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7
> 0x1A8 0x410 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD7_SAI6_MCLK
> 0x1A8 0x410 0x530 0x1 0x1
> +#define MX8MM_IOMUXC_SAI1_TXD7_PDM_CLK
> 0x1A8 0x410 0x000 0x3 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15
> 0x1A8 0x410 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19
> 0x1A8 0x410 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15
> 0x1A8 0x410 0x000 0x6 0x0
> +#define MX8MM_IOMUXC_SAI1_TXD7_SIM_M_HBURST2
> 0x1A8 0x410 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK
> 0x1AC 0x414 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI1_MCLK_SAI5_MCLK
> 0x1AC 0x414 0x52C 0x1 0x1
> +#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK
> 0x1AC 0x414 0x4C8 0x2 0x2
> +#define MX8MM_IOMUXC_SAI1_MCLK_PDM_CLK
> 0x1AC 0x414 0x000 0x3 0x0
> +#define MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20
> 0x1AC 0x414 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP
> 0x1AC 0x414 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC
> 0x1B0 0x418 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC
> 0x1B0 0x418 0x4EC 0x1 0x2
> +#define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21
> 0x1B0 0x418 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0
> 0x1B0 0x418 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK
> 0x1B4 0x41C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK
> 0x1B4 0x41C 0x4E8 0x1 0x2
> +#define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22
> 0x1B4 0x41C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1
> 0x1B4 0x41C 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0
> 0x1B8 0x420 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0
> 0x1B8 0x420 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23
> 0x1B8 0x420 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2
> 0x1B8 0x420 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC
> 0x1BC 0x424 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1
> 0x1BC 0x424 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24
> 0x1BC 0x424 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE
> 0x1BC 0x424 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK
> 0x1C0 0x428 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI2_TXC_SAI5_TX_DATA2
> 0x1C0 0x428 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25
> 0x1C0 0x428 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT
> 0x1C0 0x428 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0
> 0x1C4 0x42C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3
> 0x1C4 0x42C 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26
> 0x1C4 0x42C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI2_TXD0_TPSMP_CLK
> 0x1C4 0x42C 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK
> 0x1C8 0x430 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI2_MCLK_SAI5_MCLK
> 0x1C8 0x430 0x52C 0x1 0x2
> +#define MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27
> 0x1C8 0x430 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR
> 0x1C8 0x430 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC
> 0x1CC 0x434 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1
> 0x1CC 0x434 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC
> 0x1CC 0x434 0x4E4 0x2 0x2
> +#define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28
> 0x1CC 0x434 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0
> 0x1CC 0x434 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK
> 0x1D0 0x438 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CAPTURE2
> 0x1D0 0x438 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK
> 0x1D0 0x438 0x4D0 0x2 0x2
> +#define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29
> 0x1D0 0x438 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1
> 0x1D0 0x438 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0
> 0x1D4 0x43C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1
> 0x1D4 0x43C 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0
> 0x1D4 0x43C 0x4D4 0x2 0x2
> +#define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30
> 0x1D4 0x43C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0
> 0x1D4 0x43C 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC
> 0x1D8 0x440 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CLK
> 0x1D8 0x440 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1
> 0x1D8 0x440 0x4D8 0x2 0x2
> +#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31
> 0x1D8 0x440 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1
> 0x1D8 0x440 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK
> 0x1DC 0x444 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2
> 0x1DC 0x444 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2
> 0x1DC 0x444 0x4DC 0x2 0x2
> +#define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0
> 0x1DC 0x444 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2
> 0x1DC 0x444 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0
> 0x1E0 0x448 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI3_TXD_GPT1_COMPARE3
> 0x1E0 0x448 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI3_TXD_SAI5_RX_DATA3
> 0x1E0 0x448 0x4E0 0x2 0x2
> +#define MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1
> 0x1E0 0x448 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI3_TXD_TPSMP_HDATA3
> 0x1E0 0x448 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK
> 0x1E4 0x44C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT
> 0x1E4 0x44C 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI3_MCLK_SAI5_MCLK
> 0x1E4 0x44C 0x52C 0x2 0x3
> +#define MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2
> 0x1E4 0x44C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SAI3_MCLK_TPSMP_HDATA4
> 0x1E4 0x44C 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT
> 0x1E8 0x450 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT
> 0x1E8 0x450 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3
> 0x1E8 0x450 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SPDIF_TX_TPSMP_HDATA5
> 0x1E8 0x450 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN
> 0x1EC 0x454 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT
> 0x1EC 0x454 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4
> 0x1EC 0x454 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SPDIF_RX_TPSMP_HDATA6
> 0x1EC 0x454 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK
> 0x1F0 0x458 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT
> 0x1F0 0x458 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5
> 0x1F0 0x458 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7
> 0x1F0 0x458 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK
> 0x1F4 0x45C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX
> 0x1F4 0x45C 0x504 0x1 0x0
> +#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX
> 0x1F4 0x45C 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_ECSPI1_SCLK_GPIO5_IO6
> 0x1F4 0x45C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8
> 0x1F4 0x45C 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI
> 0x1F8 0x460 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX
> 0x1F8 0x460 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX
> 0x1F8 0x460 0x504 0x1 0x1
> +#define MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7
> 0x1F8 0x460 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9
> 0x1F8 0x460 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO
> 0x1FC 0x464 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B
> 0x1FC 0x464 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B
> 0x1FC 0x464 0x500 0x1 0x0
> +#define MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8
> 0x1FC 0x464 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10
> 0x1FC 0x464 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_ECSPI1_SS0_ECSPI1_SS0
> 0x200 0x468 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B
> 0x200 0x468 0x500 0x1 0x1
> +#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B
> 0x200 0x468 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9
> 0x200 0x468 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11
> 0x200 0x468 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK
> 0x204 0x46C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX
> 0x204 0x46C 0x50C 0x1 0x0
> +#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX
> 0x204 0x46C 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10
> 0x204 0x46C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12
> 0x204 0x46C 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI
> 0x208 0x470 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX
> 0x208 0x470 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX
> 0x208 0x470 0x50C 0x1 0x1
> +#define MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11
> 0x208 0x470 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13
> 0x208 0x470 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO
> 0x20C 0x474 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B
> 0x20C 0x474 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B
> 0x20C 0x474 0x508 0x1 0x0
> +#define MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12
> 0x20C 0x474 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14
> 0x20C 0x474 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0
> 0x210 0x478 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B
> 0x210 0x478 0x508 0x1 0x1
> +#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B
> 0x210 0x478 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13
> 0x210 0x478 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15
> 0x210 0x478 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL
> 0x214 0x47C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_I2C1_SCL_ENET1_MDC
> 0x214 0x47C 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14
> 0x214 0x47C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_I2C1_SCL_TPSMP_HDATA16
> 0x214 0x47C 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA
> 0x218 0x480 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_I2C1_SDA_ENET1_MDIO
> 0x218 0x480 0x4C0 0x1 0x2
> +#define MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15
> 0x218 0x480 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_I2C1_SDA_TPSMP_HDATA17
> 0x218 0x480 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL
> 0x21C 0x484 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN
> 0x21C 0x484 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16
> 0x21C 0x484 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_I2C2_SCL_TPSMP_HDATA18
> 0x21C 0x484 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA
> 0x220 0x488 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT
> 0x220 0x488 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17
> 0x220 0x488 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_I2C2_SDA_TPSMP_HDATA19
> 0x220 0x488 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL
> 0x224 0x48C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_I2C3_SCL_PWM4_OUT
> 0x224 0x48C 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_I2C3_SCL_GPT2_CLK
> 0x224 0x48C 0x000 0x2 0x0
> +#define MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18
> 0x224 0x48C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_I2C3_SCL_TPSMP_HDATA20
> 0x224 0x48C 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA
> 0x228 0x490 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_I2C3_SDA_PWM3_OUT
> 0x228 0x490 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_I2C3_SDA_GPT3_CLK
> 0x228 0x490 0x000 0x2 0x0
> +#define MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19
> 0x228 0x490 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_I2C3_SDA_TPSMP_HDATA21
> 0x228 0x490 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL
> 0x22C 0x494 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_I2C4_SCL_PWM2_OUT
> 0x22C 0x494 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B
> 0x22C 0x494 0x524 0x12 0x0
> +#define MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20
> 0x22C 0x494 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_I2C4_SCL_TPSMP_HDATA22
> 0x22C 0x494 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA
> 0x230 0x498 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_I2C4_SDA_PWM1_OUT
> 0x230 0x498 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B
> 0x230 0x498 0x528 0x2 0x0
> +#define MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21
> 0x230 0x498 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_I2C4_SDA_TPSMP_HDATA23
> 0x230 0x498 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX
> 0x234 0x49C 0x4F4 0x0 0x0
> +#define MX8MM_IOMUXC_UART1_RXD_UART1_DTE_TX
> 0x234 0x49C 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK
> 0x234 0x49C 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22
> 0x234 0x49C 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_UART1_RXD_TPSMP_HDATA24
> 0x234 0x49C 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX
> 0x238 0x4A0 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_UART1_TXD_UART1_DTE_RX
> 0x238 0x4A0 0x4F4 0x0 0x0
> +#define MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI
> 0x238 0x4A0 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23
> 0x238 0x4A0 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_UART1_TXD_TPSMP_HDATA25
> 0x238 0x4A0 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX
> 0x23C 0x4A4 0x4FC 0x0 0x0
> +#define MX8MM_IOMUXC_UART2_RXD_UART2_DTE_TX
> 0x23C 0x4A4 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO
> 0x23C 0x4A4 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24
> 0x23C 0x4A4 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_UART2_RXD_TPSMP_HDATA26
> 0x23C 0x4A4 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX
> 0x240 0x4A8 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_UART2_TXD_UART2_DTE_RX
> 0x240 0x4A8 0x4FC 0x0 0x1
> +#define MX8MM_IOMUXC_UART2_TXD_ECSPI3_SS0
> 0x240 0x4A8 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25
> 0x240 0x4A8 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_UART2_TXD_TPSMP_HDATA27
> 0x240 0x4A8 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX
> 0x244 0x4AC 0x504 0x0 0x2
> +#define MX8MM_IOMUXC_UART3_RXD_UART3_DTE_TX
> 0x244 0x4AC 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B
> 0x244 0x4AC 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B
> 0x244 0x4AC 0x4F0 0x1 0x0
> +#define MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26
> 0x244 0x4AC 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_UART3_RXD_TPSMP_HDATA28
> 0x244 0x4AC 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX
> 0x248 0x4B0 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_UART3_TXD_UART3_DTE_RX
> 0x248 0x4B0 0x504 0x0 0x3
> +#define MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B
> 0x248 0x4B0 0x4F0 0x1 0x1
> +#define MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B
> 0x248 0x4B0 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27
> 0x248 0x4B0 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_UART3_TXD_TPSMP_HDATA29
> 0x248 0x4B0 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX
> 0x24C 0x4B4 0x50C 0x0 0x2
> +#define MX8MM_IOMUXC_UART4_RXD_UART4_DTE_TX
> 0x24C 0x4B4 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B
> 0x24C 0x4B4 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_UART4_RXD_UART2_DTE_RTS_B
> 0x24C 0x4B4 0x4F8 0x1 0x0
> +#define MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B
> 0x24C 0x4B4 0x524 0x2 0x1
> +#define MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28
> 0x24C 0x4B4 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_UART4_RXD_TPSMP_HDATA30
> 0x24C 0x4B4 0x000 0x7 0x0
> +#define MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX
> 0x250 0x4B8 0x000 0x0 0x0
> +#define MX8MM_IOMUXC_UART4_TXD_UART4_DTE_RX
> 0x250 0x4B8 0x50C 0x0 0x3
> +#define MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B
> 0x250 0x4B8 0x4F8 0x1 0x1
> +#define MX8MM_IOMUXC_UART4_TXD_UART2_DTE_CTS_B
> 0x250 0x4B8 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B
> 0x250 0x4B8 0x528 0x2 0x1
> +#define MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29
> 0x250 0x4B8 0x000 0x5 0x0
> +#define MX8MM_IOMUXC_UART4_TXD_TPSMP_HDATA31
> 0x250 0x4B8 0x000 0x7 0x0
> +
> +#endif /* __DTS_IMX8MM_PINFUNC_H */
> --
> 1.9.1
Aisheng Dong Jan. 11, 2019, 12:33 p.m. | #2
> -----Original Message-----
> From: Jacky Bai
> Sent: Tuesday, January 8, 2019 5:05 PM
> Subject: [PATCH 2/2] pinctrl: freescale: Add imx8mm pinctrl driver support
> 
> Add the pinctrl driver support for i.MX8MM.
> 
> Signed-off-by: Bai Ping <ping.bai@nxp.com>
> ---
>  drivers/pinctrl/freescale/Kconfig          |   7 +
>  drivers/pinctrl/freescale/Makefile         |   1 +
>  drivers/pinctrl/freescale/pinctrl-imx8mm.c | 349
> +++++++++++++++++++++++++++++
>  3 files changed, 357 insertions(+)
>  create mode 100644 drivers/pinctrl/freescale/pinctrl-imx8mm.c
> 
> diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
> index 72b869d..05963a3 100644
> --- a/drivers/pinctrl/freescale/Kconfig
> +++ b/drivers/pinctrl/freescale/Kconfig
> @@ -122,6 +122,13 @@ config PINCTRL_IMX7ULP
>  	help
>  	  Say Y here to enable the imx7ulp pinctrl driver
> 
> +config PINCTRL_IMX8MM
> +	bool "IMX8MM pinctrl driver"
> +	depends on ARCH_MXC && ARM64
> +	select PINCTRL_IMX
> +	help
> +	  Say Y here to enable the imx8mm pinctrl driver
> +
>  config PINCTRL_IMX8MQ
>  	bool "IMX8MQ pinctrl driver"
>  	depends on ARCH_MXC && ARM64
> diff --git a/drivers/pinctrl/freescale/Makefile
> b/drivers/pinctrl/freescale/Makefile
> index 6ee398a..d64dc5d 100644
> --- a/drivers/pinctrl/freescale/Makefile
> +++ b/drivers/pinctrl/freescale/Makefile
> @@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_IMX6SX)	+= pinctrl-imx6sx.o
>  obj-$(CONFIG_PINCTRL_IMX6UL)	+= pinctrl-imx6ul.o
>  obj-$(CONFIG_PINCTRL_IMX7D)	+= pinctrl-imx7d.o
>  obj-$(CONFIG_PINCTRL_IMX7ULP)	+= pinctrl-imx7ulp.o
> +obj-$(CONFIG_PINCTRL_IMX8MM)	+= pinctrl-imx8mm.o
>  obj-$(CONFIG_PINCTRL_IMX8MQ)	+= pinctrl-imx8mq.o
>  obj-$(CONFIG_PINCTRL_IMX8QXP)	+= pinctrl-imx8qxp.o
>  obj-$(CONFIG_PINCTRL_VF610)	+= pinctrl-vf610.o
> diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mm.c
> b/drivers/pinctrl/freescale/pinctrl-imx8mm.c
> new file mode 100644
> index 0000000..60195a5
> --- /dev/null
> +++ b/drivers/pinctrl/freescale/pinctrl-imx8mm.c
> @@ -0,0 +1,349 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2017-2018 NXP
> + */
> +
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>

Nitpick:
seems not need this line

> +#include <linux/of.h>
> +#include <linux/of_device.h>

Ditto

> +#include <linux/pinctrl/pinctrl.h>
> +

Add <Linux/platform_device.h>

(other IMX SoCs may have the same issue, we could clean up it later)

Otherwise, you can resend with my ACK.

Regards
Dong Aisheng

> +#include "pinctrl-imx.h"
> +
> +enum imx8mm_pads {
> +	MX8MM_PAD_RESERVE0 = 0,
> +	MX8MM_PAD_RESERVE1 = 1,
> +	MX8MM_PAD_RESERVE2 = 2,
> +	MX8MM_PAD_RESERVE3 = 3,
> +	MX8MM_PAD_RESERVE4 = 4,
> +	MX8MM_PAD_RESERVE5 = 5,
> +	MX8MM_PAD_RESERVE6 = 6,
> +	MX8MM_PAD_RESERVE7 = 7,
> +	MX8MM_PAD_RESERVE8 = 8,
> +	MX8MM_PAD_RESERVE9 = 9,
> +	MX8MM_IOMUXC_GPIO1_IO00 = 10,
> +	MX8MM_IOMUXC_GPIO1_IO01 = 11,
> +	MX8MM_IOMUXC_GPIO1_IO02 = 12,
> +	MX8MM_IOMUXC_GPIO1_IO03 = 13,
> +	MX8MM_IOMUXC_GPIO1_IO04 = 14,
> +	MX8MM_IOMUXC_GPIO1_IO05 = 15,
> +	MX8MM_IOMUXC_GPIO1_IO06 = 16,
> +	MX8MM_IOMUXC_GPIO1_IO07 = 17,
> +	MX8MM_IOMUXC_GPIO1_IO08 = 18,
> +	MX8MM_IOMUXC_GPIO1_IO09 = 19,
> +	MX8MM_IOMUXC_GPIO1_IO10 = 20,
> +	MX8MM_IOMUXC_GPIO1_IO11 = 21,
> +	MX8MM_IOMUXC_GPIO1_IO12 = 22,
> +	MX8MM_IOMUXC_GPIO1_IO13 = 23,
> +	MX8MM_IOMUXC_GPIO1_IO14 = 24,
> +	MX8MM_IOMUXC_GPIO1_IO15 = 25,
> +	MX8MM_IOMUXC_ENET_MDC = 26,
> +	MX8MM_IOMUXC_ENET_MDIO = 27,
> +	MX8MM_IOMUXC_ENET_TD3 = 28,
> +	MX8MM_IOMUXC_ENET_TD2 = 29,
> +	MX8MM_IOMUXC_ENET_TD1 = 30,
> +	MX8MM_IOMUXC_ENET_TD0 = 31,
> +	MX8MM_IOMUXC_ENET_TX_CTL = 32,
> +	MX8MM_IOMUXC_ENET_TXC = 33,
> +	MX8MM_IOMUXC_ENET_RX_CTL = 34,
> +	MX8MM_IOMUXC_ENET_RXC = 35,
> +	MX8MM_IOMUXC_ENET_RD0 = 36,
> +	MX8MM_IOMUXC_ENET_RD1 = 37,
> +	MX8MM_IOMUXC_ENET_RD2 = 38,
> +	MX8MM_IOMUXC_ENET_RD3 = 39,
> +	MX8MM_IOMUXC_SD1_CLK = 40,
> +	MX8MM_IOMUXC_SD1_CMD = 41,
> +	MX8MM_IOMUXC_SD1_DATA0 = 42,
> +	MX8MM_IOMUXC_SD1_DATA1 = 43,
> +	MX8MM_IOMUXC_SD1_DATA2 = 44,
> +	MX8MM_IOMUXC_SD1_DATA3 = 45,
> +	MX8MM_IOMUXC_SD1_DATA4 = 46,
> +	MX8MM_IOMUXC_SD1_DATA5 = 47,
> +	MX8MM_IOMUXC_SD1_DATA6 = 48,
> +	MX8MM_IOMUXC_SD1_DATA7 = 49,
> +	MX8MM_IOMUXC_SD1_RESET_B = 50,
> +	MX8MM_IOMUXC_SD1_STROBE = 51,
> +	MX8MM_IOMUXC_SD2_CD_B = 52,
> +	MX8MM_IOMUXC_SD2_CLK = 53,
> +	MX8MM_IOMUXC_SD2_CMD = 54,
> +	MX8MM_IOMUXC_SD2_DATA0 = 55,
> +	MX8MM_IOMUXC_SD2_DATA1 = 56,
> +	MX8MM_IOMUXC_SD2_DATA2 = 57,
> +	MX8MM_IOMUXC_SD2_DATA3 = 58,
> +	MX8MM_IOMUXC_SD2_RESET_B = 59,
> +	MX8MM_IOMUXC_SD2_WP = 60,
> +	MX8MM_IOMUXC_NAND_ALE = 61,
> +	MX8MM_IOMUXC_NAND_CE0 = 62,
> +	MX8MM_IOMUXC_NAND_CE1 = 63,
> +	MX8MM_IOMUXC_NAND_CE2 = 64,
> +	MX8MM_IOMUXC_NAND_CE3 = 65,
> +	MX8MM_IOMUXC_NAND_CLE = 66,
> +	MX8MM_IOMUXC_NAND_DATA00 = 67,
> +	MX8MM_IOMUXC_NAND_DATA01 = 68,
> +	MX8MM_IOMUXC_NAND_DATA02 = 69,
> +	MX8MM_IOMUXC_NAND_DATA03 = 70,
> +	MX8MM_IOMUXC_NAND_DATA04 = 71,
> +	MX8MM_IOMUXC_NAND_DATA05 = 72,
> +	MX8MM_IOMUXC_NAND_DATA06 = 73,
> +	MX8MM_IOMUXC_NAND_DATA07 = 74,
> +	MX8MM_IOMUXC_NAND_DQS = 75,
> +	MX8MM_IOMUXC_NAND_RE_B = 76,
> +	MX8MM_IOMUXC_NAND_READY_B = 77,
> +	MX8MM_IOMUXC_NAND_WE_B = 78,
> +	MX8MM_IOMUXC_NAND_WP_B = 79,
> +	MX8MM_IOMUXC_SAI5_RXFS = 80,
> +	MX8MM_IOMUXC_SAI5_RXC = 81,
> +	MX8MM_IOMUXC_SAI5_RXD0 = 82,
> +	MX8MM_IOMUXC_SAI5_RXD1 = 83,
> +	MX8MM_IOMUXC_SAI5_RXD2 = 84,
> +	MX8MM_IOMUXC_SAI5_RXD3 = 85,
> +	MX8MM_IOMUXC_SAI5_MCLK = 86,
> +	MX8MM_IOMUXC_SAI1_RXFS = 87,
> +	MX8MM_IOMUXC_SAI1_RXC = 88,
> +	MX8MM_IOMUXC_SAI1_RXD0 = 89,
> +	MX8MM_IOMUXC_SAI1_RXD1 = 90,
> +	MX8MM_IOMUXC_SAI1_RXD2 = 91,
> +	MX8MM_IOMUXC_SAI1_RXD3 = 92,
> +	MX8MM_IOMUXC_SAI1_RXD4 = 93,
> +	MX8MM_IOMUXC_SAI1_RXD5 = 94,
> +	MX8MM_IOMUXC_SAI1_RXD6 = 95,
> +	MX8MM_IOMUXC_SAI1_RXD7 = 96,
> +	MX8MM_IOMUXC_SAI1_TXFS = 97,
> +	MX8MM_IOMUXC_SAI1_TXC = 98,
> +	MX8MM_IOMUXC_SAI1_TXD0 = 99,
> +	MX8MM_IOMUXC_SAI1_TXD1 = 100,
> +	MX8MM_IOMUXC_SAI1_TXD2 = 101,
> +	MX8MM_IOMUXC_SAI1_TXD3 = 102,
> +	MX8MM_IOMUXC_SAI1_TXD4 = 103,
> +	MX8MM_IOMUXC_SAI1_TXD5 = 104,
> +	MX8MM_IOMUXC_SAI1_TXD6 = 105,
> +	MX8MM_IOMUXC_SAI1_TXD7 = 106,
> +	MX8MM_IOMUXC_SAI1_MCLK = 107,
> +	MX8MM_IOMUXC_SAI2_RXFS = 108,
> +	MX8MM_IOMUXC_SAI2_RXC = 109,
> +	MX8MM_IOMUXC_SAI2_RXD0 = 110,
> +	MX8MM_IOMUXC_SAI2_TXFS = 111,
> +	MX8MM_IOMUXC_SAI2_TXC = 112,
> +	MX8MM_IOMUXC_SAI2_TXD0 = 113,
> +	MX8MM_IOMUXC_SAI2_MCLK = 114,
> +	MX8MM_IOMUXC_SAI3_RXFS = 115,
> +	MX8MM_IOMUXC_SAI3_RXC = 116,
> +	MX8MM_IOMUXC_SAI3_RXD = 117,
> +	MX8MM_IOMUXC_SAI3_TXFS = 118,
> +	MX8MM_IOMUXC_SAI3_TXC = 119,
> +	MX8MM_IOMUXC_SAI3_TXD = 120,
> +	MX8MM_IOMUXC_SAI3_MCLK = 121,
> +	MX8MM_IOMUXC_SPDIF_TX = 122,
> +	MX8MM_IOMUXC_SPDIF_RX = 123,
> +	MX8MM_IOMUXC_SPDIF_EXT_CLK = 124,
> +	MX8MM_IOMUXC_ECSPI1_SCLK = 125,
> +	MX8MM_IOMUXC_ECSPI1_MOSI = 126,
> +	MX8MM_IOMUXC_ECSPI1_MISO = 127,
> +	MX8MM_IOMUXC_ECSPI1_SS0 = 128,
> +	MX8MM_IOMUXC_ECSPI2_SCLK = 129,
> +	MX8MM_IOMUXC_ECSPI2_MOSI = 130,
> +	MX8MM_IOMUXC_ECSPI2_MISO = 131,
> +	MX8MM_IOMUXC_ECSPI2_SS0 = 132,
> +	MX8MM_IOMUXC_I2C1_SCL = 133,
> +	MX8MM_IOMUXC_I2C1_SDA = 134,
> +	MX8MM_IOMUXC_I2C2_SCL = 135,
> +	MX8MM_IOMUXC_I2C2_SDA = 136,
> +	MX8MM_IOMUXC_I2C3_SCL = 137,
> +	MX8MM_IOMUXC_I2C3_SDA = 138,
> +	MX8MM_IOMUXC_I2C4_SCL = 139,
> +	MX8MM_IOMUXC_I2C4_SDA = 140,
> +	MX8MM_IOMUXC_UART1_RXD = 141,
> +	MX8MM_IOMUXC_UART1_TXD = 142,
> +	MX8MM_IOMUXC_UART2_RXD = 143,
> +	MX8MM_IOMUXC_UART2_TXD = 144,
> +	MX8MM_IOMUXC_UART3_RXD = 145,
> +	MX8MM_IOMUXC_UART3_TXD = 146,
> +	MX8MM_IOMUXC_UART4_RXD = 147,
> +	MX8MM_IOMUXC_UART4_TXD = 148,
> +};
> +
> +/* Pad names for the pinmux subsystem */ static const struct
> +pinctrl_pin_desc imx8mm_pinctrl_pads[] = {
> +	IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE0),
> +	IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE1),
> +	IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE2),
> +	IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE3),
> +	IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE4),
> +	IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE5),
> +	IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE6),
> +	IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE7),
> +	IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE8),
> +	IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE9),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO00),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO01),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO02),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO03),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO04),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO05),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO06),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO07),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO08),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO09),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO10),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO11),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO12),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO13),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO14),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO15),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_MDC),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_MDIO),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD3),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD2),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD1),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD0),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TX_CTL),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TXC),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RX_CTL),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RXC),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD0),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD1),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD2),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD3),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_CLK),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_CMD),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA0),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA1),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA2),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA3),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA4),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA5),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA6),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA7),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_RESET_B),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_STROBE),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CD_B),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CLK),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CMD),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA0),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA1),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA2),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA3),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_RESET_B),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_WP),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_ALE),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE0),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE1),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE2),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE3),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CLE),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA00),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA01),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA02),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA03),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA04),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA05),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA06),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA07),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DQS),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_RE_B),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_READY_B),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_WE_B),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_WP_B),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXFS),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXC),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD0),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD1),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD2),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD3),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_MCLK),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXFS),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXC),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD0),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD1),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD2),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD3),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD4),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD5),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD6),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD7),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXFS),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXC),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD0),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD1),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD2),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD3),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD4),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD5),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD6),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD7),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_MCLK),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXFS),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXC),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXD0),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXFS),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXC),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXD0),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_MCLK),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXFS),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXC),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXD),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXFS),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXC),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXD),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_MCLK),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_TX),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_RX),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_EXT_CLK),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_SCLK),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_MOSI),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_MISO),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_SS0),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_SCLK),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_MOSI),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_MISO),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_SS0),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C1_SCL),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C1_SDA),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C2_SCL),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C2_SDA),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C3_SCL),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C3_SDA),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C4_SCL),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C4_SDA),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART1_RXD),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART1_TXD),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART2_RXD),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART2_TXD),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART3_RXD),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART3_TXD),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART4_RXD),
> +	IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART4_TXD),
> +};
> +
> +static const struct imx_pinctrl_soc_info imx8mm_pinctrl_info = {
> +	.pins = imx8mm_pinctrl_pads,
> +	.npins = ARRAY_SIZE(imx8mm_pinctrl_pads),
> +	.gpr_compatible = "fsl,imx8mm-iomuxc-gpr", };
> +
> +static const struct of_device_id imx8mm_pinctrl_of_match[] = {
> +	{ .compatible = "fsl,imx8mm-iomuxc", .data = &imx8mm_pinctrl_info, },
> +	{ /* sentinel */ }
> +};
> +
> +static int imx8mm_pinctrl_probe(struct platform_device *pdev) {
> +	return imx_pinctrl_probe(pdev, &imx8mm_pinctrl_info); }
> +
> +static struct platform_driver imx8mm_pinctrl_driver = {
> +	.driver = {
> +		.name = "imx8mm-pinctrl",
> +		.of_match_table = of_match_ptr(imx8mm_pinctrl_of_match),
> +		.suppress_bind_attrs = true,
> +	},
> +	.probe = imx8mm_pinctrl_probe,
> +};
> +
> +static int __init imx8mm_pinctrl_init(void) {
> +	return platform_driver_register(&imx8mm_pinctrl_driver);
> +}
> +arch_initcall(imx8mm_pinctrl_init);
> --
> 1.9.1

Patch

diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt
new file mode 100644
index 0000000..524a16f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt
@@ -0,0 +1,36 @@ 
+* Freescale IMX8MM IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
+for common binding part and usage.
+
+Required properties:
+- compatible: "fsl,imx8mm-iomuxc"
+- reg: should contain the base physical address and size of the iomuxc
+  registers.
+
+Required properties in sub-nodes:
+- fsl,pins: each entry consists of 6 integers and represents the mux and config
+  setting for one pin.  The first 5 integers <mux_reg conf_reg input_reg mux_val
+  input_val> are specified using a PIN_FUNC_ID macro, which can be found in
+  <dt-bindings/pinctrl/imx8mm-pinfunc.h>. The last integer CONFIG is
+  the pad setting value like pull-up on this pin.  Please refer to i.MX8M Mini
+  Reference Manual for detailed CONFIG settings.
+
+Examples:
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
+};
+
+iomuxc: pinctrl@30330000 {
+        compatible = "fsl,imx8mm-iomuxc";
+        reg = <0x0 0x30330000 0x0 0x10000>;
+
+        pinctrl_uart1: uart1grp {
+                fsl,pins = <
+                        MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX             0x140
+                        MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX             0x140
+                >;
+        };
+};
diff --git a/include/dt-bindings/pinctrl/imx8mm-pinfunc.h b/include/dt-bindings/pinctrl/imx8mm-pinfunc.h
new file mode 100644
index 0000000..e25f7fc
--- /dev/null
+++ b/include/dt-bindings/pinctrl/imx8mm-pinfunc.h
@@ -0,0 +1,629 @@ 
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017-2018 NXP
+ */
+
+#ifndef __DTS_IMX8MM_PINFUNC_H
+#define __DTS_IMX8MM_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+
+#define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0                                   0x028 0x290 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT          0x028 0x290 0x4C0 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K                          0x028 0x290 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1                       0x028 0x290 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL                                    0x028 0x290 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1                                   0x02C 0x294 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT                                    0x02C 0x294 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M                          0x02C 0x294 0x4BC 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2                       0x02C 0x294 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE                                  0x02C 0x294 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2                                   0x030 0x298 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B                                0x030 0x298 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY                              0x030 0x298 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO02_SJC_DE_B                                    0x030 0x298 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3                                   0x034 0x29C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT                              0x034 0x29C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0                            0x034 0x29C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK                              0x034 0x29C 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_SJC_DONE                                    0x034 0x29C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4                                   0x038 0x2A0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT                              0x038 0x2A0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1                            0x038 0x2A0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV                           0x038 0x2A0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG                            0x038 0x2A0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5                                   0x03C 0x2A4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_M4_NMI                                      0x03C 0x2A4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY                     0x03C 0x2A4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT                       0x03C 0x2A4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG                            0x03C 0x2A4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6                                   0x040 0x2A8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_ENET1_MDC                                   0x040 0x2A8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_USDHC1_CD_B                                 0x040 0x2A8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3                       0x040 0x2A8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG                            0x040 0x2A8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7                                   0x044 0x2AC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_ENET1_MDIO                                  0x044 0x2AC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_USDHC1_WP                                   0x044 0x2AC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4                       0x044 0x2AC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG                            0x044 0x2AC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8                                   0x048 0x2B0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN                        0x048 0x2B0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_USDHC2_RESET_B                              0x048 0x2B0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT                           0x048 0x2B0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG                              0x048 0x2B0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9                                   0x04C 0x2B4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT                       0x04C 0x2B4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0                            0x04C 0x2B4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP                           0x04C 0x2B4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG                           0x04C 0x2B4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10                                  0x050 0x2B8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO10_USB1_OTG_ID                                 0x050 0x2B8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED             0x050 0x2B8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11                                  0x054 0x2BC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO11_USB2_OTG_ID                                 0x054 0x2BC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY                     0x054 0x2BC 0x4BC 0x5 0x1
+#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0                           0x054 0x2BC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS                    0x054 0x2BC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12                                  0x058 0x2C0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR                                0x058 0x2C0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1                            0x058 0x2C0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1                           0x058 0x2C0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0                          0x058 0x2C0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13                                  0x05C 0x2C4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC                                 0x05C 0x2C4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT                                    0x05C 0x2C4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2                           0x05C 0x2C4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1                          0x05C 0x2C4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14                                  0x060 0x2C8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR                                0x060 0x2C8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT                                    0x060 0x2C8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1                          0x060 0x2C8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2                          0x060 0x2C8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15                                  0x064 0x2CC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC                                 0x064 0x2CC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT                                    0x064 0x2CC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2                          0x064 0x2CC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB                             0x064 0x2CC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                                     0x068 0x2D0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16                                    0x068 0x2D0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO                                   0x06C 0x2D4 0x4C0 0x0 0x1
+#define MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17                                   0x06C 0x2D4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3                               0x070 0x2D8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18                                    0x070 0x2D8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2                               0x074 0x2DC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK                                  0x074 0x2DC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19                                    0x074 0x2DC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1                               0x078 0x2E0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20                                    0x078 0x2E0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0                               0x07C 0x2E4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21                                    0x07C 0x2E4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL                         0x080 0x2E8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22                                 0x080 0x2E8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC                               0x084 0x2EC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TXC_ENET1_TX_ER                                   0x084 0x2EC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23                                    0x084 0x2EC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL                         0x088 0x2F0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24                                 0x088 0x2F0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC                               0x08C 0x2F4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER                                   0x08C 0x2F4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25                                    0x08C 0x2F4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0                               0x090 0x2F8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26                                    0x090 0x2F8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1                               0x094 0x2FC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27                                    0x094 0x2FC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2                               0x098 0x300 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28                                    0x098 0x300 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3                               0x09C 0x304 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29                                    0x09C 0x304 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK                                     0x0A0 0x308 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0                                      0x0A0 0x308 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD                                     0x0A4 0x30C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1                                      0x0A4 0x30C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0                                 0x0A8 0x310 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2                                    0x0A8 0x31  0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1                                 0x0AC 0x314 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3                                    0x0AC 0x314 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2                                 0x0B0 0x318 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4                                    0x0B0 0x318 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3                                 0x0B4 0x31C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5                                    0x0B4 0x31C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4                                 0x0B8 0x320 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6                                    0x0B8 0x320 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5                                 0x0BC 0x324 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7                                    0x0BC 0x324 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6                                 0x0C0 0x328 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8                                    0x0C0 0x328 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7                                 0x0C4 0x32C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9                                    0x0C4 0x32C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B                             0x0C8 0x330 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10                                 0x0C8 0x330 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE                               0x0CC 0x334 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11                                  0x0CC 0x334 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B                                   0x0D0 0x338 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                                    0x0D0 0x338 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                                     0x0D4 0x33C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_CLK_GPIO2_IO13                                     0x0D4 0x33C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0                          0x0D4 0x33C 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0                               0x0D4 0x33C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                                     0x0D8 0x340 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_CMD_GPIO2_IO14                                     0x0D8 0x340 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1                          0x0D8 0x340 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1                               0x0D8 0x340 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0                                 0x0DC 0x344 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_DATA0_GPIO2_IO15                                   0x0DC 0x344 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2                        0x0DC 0x344 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2                             0x0DC 0x344 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1                                 0x0E0 0x348 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_DATA1_GPIO2_IO16                                   0x0E0 0x348 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT                            0x0E0 0x348 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3                             0x0E0 0x348 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2                                 0x0E4 0x34C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_DATA2_GPIO2_IO17                                   0x0E4 0x34C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP                            0x0E4 0x34C 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4                             0x0E4 0x34C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3                                 0x0E8 0x350 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_DATA3_GPIO2_IO18                                   0x0E8 0x350 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET                     0x0E8 0x350 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B                             0x0EC 0x354 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19                                 0x0EC 0x354 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET                  0x0EC 0x354 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_WP_USDHC2_WP                                       0x0F0 0x358 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_WP_GPIO2_IO20                                      0x0F0 0x358 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_WP_SIM_M_HMASTLOCK                                 0x0F0 0x358 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE                                   0x0F4 0x35C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK                                   0x0F4 0x35C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0                                     0x0F4 0x35C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_ALE_SIM_M_HPROT0                                  0x0F4 0x35C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B                               0x0F8 0x360 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B                                0x0F8 0x360 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1                                   0x0F8 0x360 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_CE0_B_SIM_M_HPROT1                                0x0F8 0x360 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B                               0x0FC 0x364 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B                                0x0FC 0x364 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE                               0x0FC 0x364 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2                                   0x0FC 0x364 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_CE1_B_SIM_M_HPROT2                                0x0FC 0x364 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B                               0x100 0x368 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B                                0x100 0x368 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5                                0x100 0x368 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3                                   0x100 0x368 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_CE2_B_SIM_M_HPROT3                                0x100 0x368 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B                               0x104 0x36C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B                                0x104 0x36C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6                                0x104 0x36C 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4                                   0x104 0x36C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_CE3_B_SIM_M_HADDR0                                0x104 0x36C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE                                   0x108 0x370 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK                                   0x108 0x370 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7                                  0x108 0x370 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5                                     0x108 0x370 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_CLE_SIM_M_HADDR1                                  0x108 0x370 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00                             0x10C 0x374 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0                               0x10C 0x374 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6                                  0x10C 0x374 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA00_SIM_M_HADDR2                               0x10C 0x374 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01                             0x110 0x378 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1                               0x110 0x378 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7                                  0x110 0x378 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA01_SIM_M_HADDR3                               0x110 0x378 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02                             0x114 0x37C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2                               0x114 0x37C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8                                  0x114 0x37C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA02_SIM_M_HADDR4                               0x114 0x37C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03                             0x118 0x380 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3                               0x118 0x380 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9                                  0x118 0x380 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA03_SIM_M_HADDR5                               0x118 0x380 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04                             0x11C 0x384 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0                               0x11C 0x384 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0                               0x11C 0x384 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10                                 0x11C 0x384 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA04_SIM_M_HADDR6                               0x11C 0x384 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05                             0x120 0x388 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1                               0x120 0x388 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1                               0x120 0x388 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11                                 0x120 0x388 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA05_SIM_M_HADDR7                               0x120 0x388 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06                             0x124 0x38C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2                               0x124 0x38C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	                            0x124 0x38C 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12                                 0x124 0x38C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA06_SIM_M_HADDR8                               0x124 0x38C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07                             0x128 0x390 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3                               0x128 0x390 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3                               0x128 0x390 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13                                 0x128 0x390 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA07_SIM_M_HADDR9                               0x128 0x390 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DQS_RAWNAND_DQS                                   0x12C 0x394 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS                                    0x12C 0x394 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14                                    0x12C 0x394 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DQS_SIM_M_HADDR10                                 0x12C 0x394 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B                                 0x130 0x398 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_RE_B_QSPI_B_DQS                                   0x130 0x398 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4                                 0x130 0x398 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15                                   0x130 0x398 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11                                0x130 0x398 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B                           0x134 0x39C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16                                0x134 0x39C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12                             0x134 0x39C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B                                 0x138 0x3A0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK                                   0x138 0x3A0 0x000 0x12 0x0
+#define MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17                                   0x138 0x3A0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_WE_B_SIM_M_HADDR13                                0x138 0x3A0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B                                 0x13C 0x3A4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD                                   0x13C 0x3A4 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18                                   0x13C 0x3A4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_WP_B_SIM_M_HADDR14                                0x13C 0x3A4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC                                 0x140 0x3A8 0x4E4 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0                                0x140 0x3A8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19                                   0x140 0x3A8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK                                  0x144 0x3AC 0x4D0 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXC_SAI1_TX_DATA1                                 0x144 0x3AC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXC_PDM_CLK                                       0x144 0x3AC 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20                                    0x144 0x3AC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0                                0x148 0x3B0 0x4D4 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2                                0x148 0x3B0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0                                    0x148 0x3B0 0x534 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21                                   0x148 0x3B0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1                                0x14C 0x3B4 0x4D8 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3                                0x14C 0x3B4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC                                 0x14C 0x3B4 0x4CC 0x2 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC                                 0x14C 0x3B4 0x4EC 0x3 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1                                    0x14C 0x3B4 0x538 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22                                   0x14C 0x3B4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2                                0x150 0x3B8 0x4DC 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4                                0x150 0x3B8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC                                 0x150 0x3B8 0x4CC 0x2 0x1
+#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK                                 0x150 0x3B8 0x4E8 0x3 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2                                    0x150 0x3B8 0x53c 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23                                   0x150 0x3B8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3                                0x154 0x3BC 0x4E0 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5                                0x154 0x3BC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC                                 0x154 0x3BC 0x4CC 0x2 0x2
+#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0                                0x154 0x3BC 0x000 0x3 0x0
+#define MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3                                    0x154 0x3BC 0x540 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24                                   0x154 0x3BC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK                                    0x158 0x3C0 0x52C 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK                                 0x158 0x3C0 0x4C8 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_MCLK_SAI4_MCLK                                    0x158 0x3C0 0x000 0x2 0x0
+#define MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25                                   0x158 0x3C0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK                      0x158 0x3C0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC                                 0x15C 0x3C4 0x4C4 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC                                 0x15C 0x3C4 0x4E4 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK                          0x15C 0x3C4 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0                                    0x15C 0x3C4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXFS_SIM_M_HADDR15                                0x15C 0x3C4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK                                  0x160 0x3C8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXC_SAI5_RX_BCLK                                  0x160 0x3C8 0x4D0 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL                           0x160 0x3C8 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1                                     0x160 0x3C8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXC_SIM_M_HADDR16                                 0x160 0x3C8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0                                0x164 0x3CC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0                                0x164 0x3CC 0x4D4 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_RXD0_PDM_DATA0                                    0x164 0x3CC 0x534 0x3 0x1
+#define MX8MM_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0                             0x164 0x3CC 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2                                    0x164 0x3CC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0                       0x164 0x3CC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD0_SIM_M_HADDR17                                0x164 0x3CC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1                                0x168 0x3D0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1                                0x168 0x3D0 0x4D8 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_RXD1_PDM_DATA1                                    0x168 0x3D0 0x538 0x3 0x1
+#define MX8MM_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1                             0x168 0x3D0 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3                                    0x168 0x3D0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1                       0x168 0x3D0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD1_SIM_M_HADDR18                                0x168 0x3D0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2                                0x16C 0x3D4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2                                0x16C 0x3D4 0x4DC 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_RXD2_PDM_DATA2                                    0x16C 0x3D4 0x53C 0x3 0x1
+#define MX8MM_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2                             0x16C 0x3D4 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4                                    0x16C 0x3D4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2                       0x16C 0x3D4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD2_SIM_M_HADDR19                                0x16C 0x3D4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3                                0x170 0x3D8 0x4E0 0x0 0x1
+#define MX8MM_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3                                0x170 0x3D8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_RXD3_PDM_DATA3                                    0x170 0x3D8 0x540 0x3 0x1
+#define MX8MM_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3                             0x170 0x3D8 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5                                    0x170 0x3D8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3                       0x170 0x3D8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD3_SIM_M_HADDR20                                0x170 0x3D8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4                                0x174 0x3DC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK                                 0x174 0x3DC 0x51C 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK                                 0x174 0x3DC 0x510 0x2 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4                             0x174 0x3DC 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6                                    0x174 0x3DC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4                       0x174 0x3DC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_SIM_M_HADDR21                                0x174 0x3DC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5                                0x178 0x3E0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0                                0x178 0x3E0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0                                0x178 0x3E0 0x514 0x2 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC                                 0x178 0x3E0 0x4C4 0x3 0x1
+#define MX8MM_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5                             0x178 0x3E0 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7                                    0x178 0x3E0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5                       0x178 0x3E0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_SIM_M_HADDR22                                0x178 0x3E0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6                                0x17C 0x3E4 0x520 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC                                 0x17C 0x3E4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC                                 0x17C 0x3E4 0x518 0x2 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6                             0x17C 0x3E4 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8                                    0x17C 0x3E4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6                       0x17C 0x3E4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_SIM_M_HADDR23                                0x17C 0x3E4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7                                0x180 0x3E8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_SAI6_MCLK                                    0x180 0x3E8 0x530 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC                                 0x180 0x3E8 0x4CC 0x2 0x4
+#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4                                0x180 0x3E8 0x000 0x3 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7                             0x180 0x3E8 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9                                    0x180 0x3E8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7                       0x180 0x3E8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_SIM_M_HADDR24                                0x180 0x3E8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC                                 0x184 0x3EC 0x4CC 0x0 0x3
+#define MX8MM_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC                                 0x184 0x3EC 0x4EC 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO                             0x184 0x3EC 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10                                   0x184 0x3EC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXFS_SIM_M_HADDR25                                0x184 0x3EC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK                                  0x188 0x3F0 0x4C8 0x0 0x1
+#define MX8MM_IOMUXC_SAI1_TXC_SAI5_TX_BCLK                                  0x188 0x3F0 0x4E8 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI                              0x188 0x3F0 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11                                    0x188 0x3F0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXC_SIM_M_HADDR26                                 0x188 0x3F0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0                                0x18C 0x3F4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0                                0x18C 0x3F4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8                             0x18C 0x3F4 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12                                   0x18C 0x3F4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8                       0x18C 0x3F4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_SIM_M_HADDR27                                0x18C 0x3F4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1                                0x190 0x3F8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1                                0x190 0x3F8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9                             0x190 0x3F8 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13                                   0x190 0x3F8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9                       0x190 0x3F8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_SIM_M_HADDR28                                0x190 0x3F8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2                                0x194 0x3FC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2                                0x194 0x3FC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10                            0x194 0x3FC 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14                                   0x194 0x3FC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10                      0x194 0x3FC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_SIM_M_HADDR29                                0x194 0x3FC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3                                0x198 0x400 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3                                0x198 0x400 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11                            0x198 0x400 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15                                   0x198 0x400 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11                      0x198 0x400 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_SIM_M_HADDR30                                0x198 0x400 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4                                0x19C 0x404 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK                                 0x19C 0x404 0x510 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK                                 0x19C 0x404 0x51C 0x2 0x1
+#define MX8MM_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12                            0x19C 0x404 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16                                   0x19C 0x404 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12                      0x19C 0x404 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD4_SIM_M_HADDR31                                0x19C 0x404 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5                                0x1A0 0x408 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0                                0x1A0 0x408 0x514 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0                                0x1A0 0x408 0x000 0x2 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13                            0x1A0 0x408 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17                                   0x1A0 0x408 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13                      0x1A0 0x408 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_SIM_M_HBURST0                                0x1A0 0x408 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6                                0x1A4 0x40C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC                                 0x1A4 0x40C 0x518 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC                                 0x1A4 0x40C 0x520 0x2 0x1
+#define MX8MM_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14                            0x1A4 0x40C 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18                                   0x1A4 0x40C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14                      0x1A4 0x40C 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD6_SIM_M_HBURST1                                0x1A4 0x40C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7                                0x1A8 0x410 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_SAI6_MCLK                                    0x1A8 0x410 0x530 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXD7_PDM_CLK                                      0x1A8 0x410 0x000 0x3 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15                            0x1A8 0x410 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19                                   0x1A8 0x410 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15                      0x1A8 0x410 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_SIM_M_HBURST2                                0x1A8 0x410 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK                                    0x1AC 0x414 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_MCLK_SAI5_MCLK                                    0x1AC 0x414 0x52C 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK                                 0x1AC 0x414 0x4C8 0x2 0x2
+#define MX8MM_IOMUXC_SAI1_MCLK_PDM_CLK                                      0x1AC 0x414 0x000 0x3 0x0
+#define MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20                                   0x1AC 0x414 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP                                  0x1AC 0x414 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC                                 0x1B0 0x418 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC                                 0x1B0 0x418 0x4EC 0x1 0x2
+#define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21                                   0x1B0 0x418 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0                                 0x1B0 0x418 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK                                  0x1B4 0x41C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK                                  0x1B4 0x41C 0x4E8 0x1 0x2
+#define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22                                    0x1B4 0x41C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1                                  0x1B4 0x41C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0                                0x1B8 0x420 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0                                0x1B8 0x420 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23                                   0x1B8 0x420 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2                                 0x1B8 0x420 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC                                 0x1BC 0x424 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1                                0x1BC 0x424 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24                                   0x1BC 0x424 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE                                 0x1BC 0x424 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK                                  0x1C0 0x428 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_TXC_SAI5_TX_DATA2                                 0x1C0 0x428 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25                                    0x1C0 0x428 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT                               0x1C0 0x428 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0                                0x1C4 0x42C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3                                0x1C4 0x42C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26                                   0x1C4 0x42C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_TXD0_TPSMP_CLK                                    0x1C4 0x42C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK                                    0x1C8 0x430 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_MCLK_SAI5_MCLK                                    0x1C8 0x430 0x52C 0x1 0x2
+#define MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27                                   0x1C8 0x430 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR                              0x1C8 0x430 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC                                 0x1CC 0x434 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1                                0x1CC 0x434 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC                                 0x1CC 0x434 0x4E4 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28                                   0x1CC 0x434 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0                                0x1CC 0x434 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK                                  0x1D0 0x438 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CAPTURE2                                 0x1D0 0x438 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK                                  0x1D0 0x438 0x4D0 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29                                    0x1D0 0x438 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1                                 0x1D0 0x438 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0                                 0x1D4 0x43C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1                                 0x1D4 0x43C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0                                 0x1D4 0x43C 0x4D4 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30                                    0x1D4 0x43C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0                                  0x1D4 0x43C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC                                 0x1D8 0x440 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CLK                                     0x1D8 0x440 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1                                0x1D8 0x440 0x4D8 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31                                   0x1D8 0x440 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1                                 0x1D8 0x440 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK                                  0x1DC 0x444 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2                                 0x1DC 0x444 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2                                 0x1DC 0x444 0x4DC 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0                                     0x1DC 0x444 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2                                  0x1DC 0x444 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0                                 0x1E0 0x448 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_TXD_GPT1_COMPARE3                                 0x1E0 0x448 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_TXD_SAI5_RX_DATA3                                 0x1E0 0x448 0x4E0 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1                                     0x1E0 0x448 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_TXD_TPSMP_HDATA3                                  0x1E0 0x448 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK                                    0x1E4 0x44C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT                                     0x1E4 0x44C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_MCLK_SAI5_MCLK                                    0x1E4 0x44C 0x52C 0x2 0x3
+#define MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2                                    0x1E4 0x44C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_MCLK_TPSMP_HDATA4                                 0x1E4 0x44C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT                                    0x1E8 0x450 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT                                      0x1E8 0x450 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3                                     0x1E8 0x450 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SPDIF_TX_TPSMP_HDATA5                                  0x1E8 0x450 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN                                     0x1EC 0x454 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT                                      0x1EC 0x454 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4                                     0x1EC 0x454 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SPDIF_RX_TPSMP_HDATA6                                  0x1EC 0x454 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK                           0x1F0 0x458 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT                                 0x1F0 0x458 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5                                0x1F0 0x458 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7                             0x1F0 0x458 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK                                0x1F4 0x45C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX                               0x1F4 0x45C 0x504 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX                               0x1F4 0x45C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_SCLK_GPIO5_IO6                                  0x1F4 0x45C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8                               0x1F4 0x45C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI                                0x1F8 0x460 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX                               0x1F8 0x460 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX                               0x1F8 0x460 0x504 0x1 0x1
+#define MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7                                  0x1F8 0x460 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9                               0x1F8 0x460 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO                                0x1FC 0x464 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B                            0x1FC 0x464 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B                            0x1FC 0x464 0x500 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8                                  0x1FC 0x464 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10                              0x1FC 0x464 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI1_SS0_ECSPI1_SS0                                  0x200 0x468 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B                             0x200 0x468 0x500 0x1 0x1
+#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B                             0x200 0x468 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9                                   0x200 0x468 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11                               0x200 0x468 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK                                0x204 0x46C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX                               0x204 0x46C 0x50C 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX                               0x204 0x46C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10                                 0x204 0x46C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12                              0x204 0x46C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI                                0x208 0x470 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX                               0x208 0x470 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX                               0x208 0x470 0x50C 0x1 0x1
+#define MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11                                 0x208 0x470 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13                              0x208 0x470 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO                                0x20C 0x474 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B                            0x20C 0x474 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B                            0x20C 0x474 0x508 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12                                 0x20C 0x474 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14                              0x20C 0x474 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0                                  0x210 0x478 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B                             0x210 0x478 0x508 0x1 0x1
+#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B                             0x210 0x478 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13                                  0x210 0x478 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15                               0x210 0x478 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL                                      0x214 0x47C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C1_SCL_ENET1_MDC                                     0x214 0x47C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14                                    0x214 0x47C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C1_SCL_TPSMP_HDATA16                                 0x214 0x47C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA                                      0x218 0x480 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C1_SDA_ENET1_MDIO                                    0x218 0x480 0x4C0 0x1 0x2
+#define MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15                                    0x218 0x480 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C1_SDA_TPSMP_HDATA17                                 0x218 0x480 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL                                      0x21C 0x484 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN                          0x21C 0x484 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16                                    0x21C 0x484 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C2_SCL_TPSMP_HDATA18                                 0x21C 0x484 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA                                      0x220 0x488 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT                         0x220 0x488 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17                                    0x220 0x488 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C2_SDA_TPSMP_HDATA19                                 0x220 0x488 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL                                      0x224 0x48C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C3_SCL_PWM4_OUT                                      0x224 0x48C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C3_SCL_GPT2_CLK                                      0x224 0x48C 0x000 0x2 0x0
+#define MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18                                    0x224 0x48C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C3_SCL_TPSMP_HDATA20                                 0x224 0x48C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA                                      0x228 0x490 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C3_SDA_PWM3_OUT                                      0x228 0x490 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C3_SDA_GPT3_CLK                                      0x228 0x490 0x000 0x2 0x0
+#define MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19                                    0x228 0x490 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C3_SDA_TPSMP_HDATA21                                 0x228 0x490 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL                                      0x22C 0x494 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C4_SCL_PWM2_OUT                                      0x22C 0x494 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B                                0x22C 0x494 0x524 0x12 0x0
+#define MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20                                    0x22C 0x494 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C4_SCL_TPSMP_HDATA22                                 0x22C 0x494 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA                                      0x230 0x498 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C4_SDA_PWM1_OUT                                      0x230 0x498 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B                                0x230 0x498 0x528 0x2 0x0
+#define MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21                                    0x230 0x498 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C4_SDA_TPSMP_HDATA23                                 0x230 0x498 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX                                 0x234 0x49C 0x4F4 0x0 0x0
+#define MX8MM_IOMUXC_UART1_RXD_UART1_DTE_TX                                 0x234 0x49C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK                                  0x234 0x49C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22                                   0x234 0x49C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART1_RXD_TPSMP_HDATA24                                0x234 0x49C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX                                 0x238 0x4A0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART1_TXD_UART1_DTE_RX                                 0x238 0x4A0 0x4F4 0x0 0x0
+#define MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI                                  0x238 0x4A0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23                                   0x238 0x4A0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART1_TXD_TPSMP_HDATA25                                0x238 0x4A0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX                                 0x23C 0x4A4 0x4FC 0x0 0x0
+#define MX8MM_IOMUXC_UART2_RXD_UART2_DTE_TX                                 0x23C 0x4A4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO                                  0x23C 0x4A4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24                                   0x23C 0x4A4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART2_RXD_TPSMP_HDATA26                                0x23C 0x4A4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX                                 0x240 0x4A8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART2_TXD_UART2_DTE_RX                                 0x240 0x4A8 0x4FC 0x0 0x1
+#define MX8MM_IOMUXC_UART2_TXD_ECSPI3_SS0                                   0x240 0x4A8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25                                   0x240 0x4A8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART2_TXD_TPSMP_HDATA27                                0x240 0x4A8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX                                 0x244 0x4AC 0x504 0x0 0x2
+#define MX8MM_IOMUXC_UART3_RXD_UART3_DTE_TX                                 0x244 0x4AC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B                              0x244 0x4AC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B                              0x244 0x4AC 0x4F0 0x1 0x0
+#define MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26                                   0x244 0x4AC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART3_RXD_TPSMP_HDATA28                                0x244 0x4AC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX                                 0x248 0x4B0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART3_TXD_UART3_DTE_RX                                 0x248 0x4B0 0x504 0x0 0x3
+#define MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B                              0x248 0x4B0 0x4F0 0x1 0x1
+#define MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B                              0x248 0x4B0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27                                   0x248 0x4B0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART3_TXD_TPSMP_HDATA29                                0x248 0x4B0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX                                 0x24C 0x4B4 0x50C 0x0 0x2
+#define MX8MM_IOMUXC_UART4_RXD_UART4_DTE_TX                                 0x24C 0x4B4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B                              0x24C 0x4B4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART4_RXD_UART2_DTE_RTS_B                              0x24C 0x4B4 0x4F8 0x1 0x0
+#define MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B                               0x24C 0x4B4 0x524 0x2 0x1
+#define MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28                                   0x24C 0x4B4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART4_RXD_TPSMP_HDATA30                                0x24C 0x4B4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX                                 0x250 0x4B8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART4_TXD_UART4_DTE_RX                                 0x250 0x4B8 0x50C 0x0 0x3
+#define MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B                              0x250 0x4B8 0x4F8 0x1 0x1
+#define MX8MM_IOMUXC_UART4_TXD_UART2_DTE_CTS_B                              0x250 0x4B8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B                               0x250 0x4B8 0x528 0x2 0x1
+#define MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29                                   0x250 0x4B8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART4_TXD_TPSMP_HDATA31                                0x250 0x4B8 0x000 0x7 0x0
+
+#endif /* __DTS_IMX8MM_PINFUNC_H */