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Mon, 7 Jan 2019 03:18:06 +0000 Received: from VI1PR04MB4414.eurprd04.prod.outlook.com ([fe80::f1e0:df54:f9c:b4b9]) by VI1PR04MB4414.eurprd04.prod.outlook.com ([fe80::f1e0:df54:f9c:b4b9%3]) with mapi id 15.20.1495.011; Mon, 7 Jan 2019 03:18:06 +0000 From: Ye Li To: "sbabic@denx.de" , "u-boot@lists.denx.de" , Peng Fan Thread-Topic: [PATCH] mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue Thread-Index: AQHUpjebhPXOPtD2QU+yVyeH/nBDow== Date: Mon, 7 Jan 2019 03:18:06 +0000 Message-ID: <1546831070-9279-1-git-send-email-ye.li@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR04CA0057.apcprd04.prod.outlook.com (2603:1096:202:14::25) To VI1PR04MB4414.eurprd04.prod.outlook.com (2603:10a6:803:6e::25) authentication-results: spf=none (sender IP is ) smtp.mailfrom=ye.li@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.68] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; 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DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR04MB3197; H:VI1PR04MB4414.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: VhDNdEwBKkI1Xy0Jt4LcuHAPOYiZ3V+djyMheEcrgjmwAkWsxE5zxYmlJ9LQeIMSqwI/6ae9JZgZQwy1a7N2xUuil6DLGEq2dCTyqzOBLKLf8ZvmrWgYPS2x8uCyLvgkY30NudUL6IJrFoIsr5FQ8PGDu7ZNJ80/Sj2X7MWUx+O0ir9zzj46nVWaqQ3kJUSNAo0+CSVUjM4SsrYv2jQf+lsv+ElSriO3G2bJFP04etUl5rhBM0NaA0TZ7+9tSNMO+F0oMgjaPf2uDn/hpAjrHA3/OWoKyuQSm1Ph6s6cWW0U8VWeFcgQ38Yk1aaQzT4f spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 75680a8c-e81b-42d9-9ddd-08d6744ebdb1 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Jan 2019 03:18:03.2215 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB3197 Cc: Fabio Estevam , dl-uboot-imx Subject: [U-Boot] [PATCH] mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode, the output clock rate is half of the internal clock rate. This patch set the DDR_EN bit first for DDR mode, hardware divide the usdhc clock automatically, then follow the original sdr clock setting method. Signed-off-by: Haibo Chen Signed-off-by: Ye Li --- drivers/mmc/fsl_esdhc.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 74007e2..87273c8 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -585,18 +585,31 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) #else int pre_div = 2; #endif - int ddr_pre_div = mmc->ddr_mode ? 2 : 1; int sdhc_clk = priv->sdhc_clk; uint clk; + /* + * For ddr mode, usdhc need to enable DDR mode first, after select + * this DDR mode, usdhc will automatically divide the usdhc clock + */ + if (mmc->ddr_mode) { + writel(readl(®s->mixctrl) | MIX_CTRL_DDREN, ®s->mixctrl); + sdhc_clk >>= 1; + } + if (clock < mmc->cfg->f_min) clock = mmc->cfg->f_min; - while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) - pre_div *= 2; + if (sdhc_clk / 16 > clock) { + for (; pre_div < 256; pre_div *= 2) + if ((sdhc_clk / pre_div) <= (clock * 16)) + break; + } else + pre_div = 1; - while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) - div++; + for (div = 1; div <= 16; div++) + if ((sdhc_clk / (div * pre_div)) <= clock) + break; pre_div >>= 1; div -= 1;