[v2,5/5] ARM: dts: qcom: msm8974: add interrupt controller properties

Message ID 20190107021145.6370-6-masneyb@onstation.org
State New
Headers show
Series
  • qcom: spmi: add support for hierarchical IRQ chip
Related show

Commit Message

Brian Masney Jan. 7, 2019, 2:11 a.m.
Add interrupt controller properties now that spmi-gpio is a proper
hierarchical IRQ chip. The interrupts property is no longer needed so
remove it.

Signed-off-by: Brian Masney <masneyb@onstation.org>
---
Changes since v1:
- Interrupts are now two cells instead of four cells.
- Drop unnecessary interrupts property.

 arch/arm/boot/dts/qcom-pm8941.dtsi | 39 +++---------------------------
 1 file changed, 3 insertions(+), 36 deletions(-)

Comments

Stephen Boyd Jan. 7, 2019, 11:51 p.m. | #1
Quoting Brian Masney (2019-01-06 18:11:45)
> -                                    <0 0xde 0 IRQ_TYPE_NONE>,
> -                                    <0 0xdf 0 IRQ_TYPE_NONE>,
> -                                    <0 0xe0 0 IRQ_TYPE_NONE>,
> -                                    <0 0xe1 0 IRQ_TYPE_NONE>,
> -                                    <0 0xe2 0 IRQ_TYPE_NONE>,
> -                                    <0 0xe3 0 IRQ_TYPE_NONE>;
> +                       interrupt-parent = <&spmi_bus>;

If I'm reading of_irq_find_parent() correctly, we don't need to specify
this? It becomes implicit because spmi_bus has the interrupt-cells
property and this is a child node of that.

> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
>  
>                         boost_bypass_n_pin: boost-bypass {
>                                 pins = "gpio21";

Patch

diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi
index 2515c5c217ac..16e6b4272d16 100644
--- a/arch/arm/boot/dts/qcom-pm8941.dtsi
+++ b/arch/arm/boot/dts/qcom-pm8941.dtsi
@@ -64,42 +64,9 @@ 
 			reg = <0xc000>;
 			gpio-controller;
 			#gpio-cells = <2>;
-			interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
-				     <0 0xc1 0 IRQ_TYPE_NONE>,
-				     <0 0xc2 0 IRQ_TYPE_NONE>,
-				     <0 0xc3 0 IRQ_TYPE_NONE>,
-				     <0 0xc4 0 IRQ_TYPE_NONE>,
-				     <0 0xc5 0 IRQ_TYPE_NONE>,
-				     <0 0xc6 0 IRQ_TYPE_NONE>,
-				     <0 0xc7 0 IRQ_TYPE_NONE>,
-				     <0 0xc8 0 IRQ_TYPE_NONE>,
-				     <0 0xc9 0 IRQ_TYPE_NONE>,
-				     <0 0xca 0 IRQ_TYPE_NONE>,
-				     <0 0xcb 0 IRQ_TYPE_NONE>,
-				     <0 0xcc 0 IRQ_TYPE_NONE>,
-				     <0 0xcd 0 IRQ_TYPE_NONE>,
-				     <0 0xce 0 IRQ_TYPE_NONE>,
-				     <0 0xcf 0 IRQ_TYPE_NONE>,
-				     <0 0xd0 0 IRQ_TYPE_NONE>,
-				     <0 0xd1 0 IRQ_TYPE_NONE>,
-				     <0 0xd2 0 IRQ_TYPE_NONE>,
-				     <0 0xd3 0 IRQ_TYPE_NONE>,
-				     <0 0xd4 0 IRQ_TYPE_NONE>,
-				     <0 0xd5 0 IRQ_TYPE_NONE>,
-				     <0 0xd6 0 IRQ_TYPE_NONE>,
-				     <0 0xd7 0 IRQ_TYPE_NONE>,
-				     <0 0xd8 0 IRQ_TYPE_NONE>,
-				     <0 0xd9 0 IRQ_TYPE_NONE>,
-				     <0 0xda 0 IRQ_TYPE_NONE>,
-				     <0 0xdb 0 IRQ_TYPE_NONE>,
-				     <0 0xdc 0 IRQ_TYPE_NONE>,
-				     <0 0xdd 0 IRQ_TYPE_NONE>,
-				     <0 0xde 0 IRQ_TYPE_NONE>,
-				     <0 0xdf 0 IRQ_TYPE_NONE>,
-				     <0 0xe0 0 IRQ_TYPE_NONE>,
-				     <0 0xe1 0 IRQ_TYPE_NONE>,
-				     <0 0xe2 0 IRQ_TYPE_NONE>,
-				     <0 0xe3 0 IRQ_TYPE_NONE>;
+			interrupt-parent = <&spmi_bus>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
 
 			boost_bypass_n_pin: boost-bypass {
 				pins = "gpio21";