From patchwork Fri Jan 4 03:07:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1020598 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Yv4Dl1F7"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43W8qJ20TGz9rxp for ; Fri, 4 Jan 2019 14:07:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727076AbfADDHz (ORCPT ); Thu, 3 Jan 2019 22:07:55 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:12348 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726073AbfADDHz (ORCPT ); Thu, 3 Jan 2019 22:07:55 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 03 Jan 2019 19:07:34 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 03 Jan 2019 19:07:54 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 03 Jan 2019 19:07:54 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 4 Jan 2019 03:07:54 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 4 Jan 2019 03:07:54 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Fri, 4 Jan 2019 03:07:54 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 03 Jan 2019 19:07:54 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo Subject: [PATCH V4 20/20] arm64: defconfig: Enable MAX8973 regulator Date: Fri, 4 Jan 2019 11:07:02 +0800 Message-ID: <20190104030702.8684-21-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190104030702.8684-1-josephl@nvidia.com> References: <20190104030702.8684-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1546571254; bh=s8rNqn2Eum1VPFV92RUUf7lj2miMv3DKkWREHAp9cZk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=Yv4Dl1F7ht/oNixGJOKKtNCHA4yaQhtXIbsepxfwUl6QNkHcT083VkfSFRfTfgivB 72EmVwI5eYgKvm6GDB4/DEOJYAUrSCk9hTFFMsCRoTSg7y5MNEE76VgDWbRpTuHVHf O2ghyC8HoEUY5ey2+637xXLHs/S0X7xMko+d/Nmc9wtItZFyYbaI300jP2ESp8eL0X 2xgtkdgZrLRc4LGQnugGJpZI5GE7gixwcdZZ3ljATPJc9NbK4aAVnteOtLvEDcyg8G 5tSuEr4iuUVm0LE84/qYFFPH+crYoqVLpedzBMIEVyPi57POchT9tzeeqX20/FmUCC xUi3h/JM+OnWg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tegra210 Smaug board uses MAX77621 for both CPU & GPU rail. Note that max8973 and max77621 share the same driver. So enable this driver for the PMIC. Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- *V4: - no change *V3: - no change *V2: - add ack tag --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 3ef443cfbab6..74d5273ba20f 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -437,6 +437,7 @@ CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_HI6421V530=y CONFIG_REGULATOR_HI655X=y CONFIG_REGULATOR_MAX77620=y +CONFIG_REGULATOR_MAX8973=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_QCOM_RPMH=y CONFIG_REGULATOR_QCOM_SMD_RPM=y