From patchwork Thu Dec 27 06:13:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 1018797 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Lz7xzfib"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43QKMC4Z6Pz9sLt for ; Thu, 27 Dec 2018 17:15:19 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728330AbeL0GPG (ORCPT ); Thu, 27 Dec 2018 01:15:06 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:34504 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729979AbeL0GOd (ORCPT ); Thu, 27 Dec 2018 01:14:33 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id wBR6Do56033468; Thu, 27 Dec 2018 00:13:50 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1545891230; bh=+9HYKdz28DvpD1a0BlSqRzAAN2Tfpb9Ur5Y+Oeyr5Fo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Lz7xzfibWsJMcLZ6bUaDFXTrIC0a+HWx8JcynB8lKYxi7KiE5HevwmjAirpOuZjXG eCakzoKdtIVkESUXyjwd/AtcVwj66dYApeRp2htJxCyo7sA2ip1wZNppYCI4bQPlSg GeBfn4VSDYNmeLmuMiC5wMwEfsjWpp+c3EKrFXq0= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wBR6Do6H125545 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 27 Dec 2018 00:13:50 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 27 Dec 2018 00:13:50 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 27 Dec 2018 00:13:50 -0600 Received: from uda0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wBR6DRrC026064; Thu, 27 Dec 2018 00:13:46 -0600 From: Lokesh Vutla To: , Nishanth Menon , Santosh Shilimkar , Rob Herring , , CC: Linux ARM Mailing List , , Tero Kristo , Sekhar Nori , Device Tree Mailing List , Peter Ujfalusi , Lokesh Vutla Subject: [PATCH v4 06/13] dt-bindings: irqchip: Introduce TISCI Interrupt router bindings Date: Thu, 27 Dec 2018 11:43:06 +0530 Message-ID: <20181227061313.5451-6-lokeshvutla@ti.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181227061313.5451-1-lokeshvutla@ti.com> References: <20181227060829.5080-1-lokeshvutla@ti.com> <20181227061313.5451-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the DT binding documentation for Interrupt router driver. Signed-off-by: Lokesh Vutla --- .../interrupt-controller/ti,sci-intr.txt | 85 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt new file mode 100644 index 000000000000..4b0ca797fda1 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt @@ -0,0 +1,85 @@ +Texas Instruments K3 Interrupt Router +===================================== + +The Interrupt Router (INTR) module provides a mechanism to mux M +interrupt inputs to N interrupt outputs, where all M inputs are selectable +to be driven per N output. There is one register per output (MUXCNTL_N) that +controls the selection. + + + Interrupt Router + +----------------------+ + | Inputs Outputs | + +-------+ | +------+ | + | GPIO |----------->| | irq0 | | Host IRQ + +-------+ | +------+ | controller + | . +-----+ | +-------+ + +-------+ | . | 0 | |----->| IRQ | + | INTA |----------->| . +-----+ | +-------+ + +-------+ | . . | + | +------+ . | + | | irqM | +-----+ | + | +------+ | N | | + | +-----+ | + +----------------------+ + +Configuration of these MUXCNTL_N registers is done by a system controller +(like the Device Memory and Security Controller on K3 AM654 SoC). System +controller will keep track of the used and unused registers within the Router. +Driver should request the system controller to get the range of GIC IRQs +assigned to the requesting hosts. It is the drivers responsibility to keep +track of Host IRQs. + +Communication between the host processor running an OS and the system +controller happens through a protocol called TI System Control Interface +(TISCI protocol). For more details refer: +Documentation/devicetree/bindings/arm/keystone/ti,sci.txt + +TISCI Interrupt Router Node: +---------------------------- +- compatible: Must be "ti,sci-intr". +- interrupt-controller: Identifies the node as an interrupt controller +- #interrupt-cells: Specifies the number of cells needed to encode an + interrupt source. The value should be 4. + First cell should contain the TISCI device ID of source + Second cell should contain the interrupt source offset + within the device + Third cell specifies the trigger type as defined + in interrupts.txt in this directory. + Fourth cell should be 1 if the irq is coming from + interrupt aggregator else 0. +- ti,sci: Phandle to TI-SCI compatible System controller node. +- ti,sci-dst-id: TISCI device ID of the destination IRQ controller. +- ti,sci-rm-range-girq: Array of TISCI subtype ids representing the host irqs + assigned to this interrupt router. Each subtype id + corresponds to a range of host irqs. + +For more details on TISCI IRQ resource management refer: +http://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_irq.html + +Example: +-------- +The following example demonstrates both interrupt router node and the consumer +node(main gpio) on the AM654 SoC: + +main_intr: interrupt-controller0 { + compatible = "ti,sci-intr"; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <4>; + ti,sci = <&dmsc>; + ti,sci-dst-id = <56>; + ti,sci-rm-range-girq = <0x1>; +}; + +main_gpio0: gpio@600000 { + ... + interrupt-parent = <&main_intr>; + interrupts = <57 256 IRQ_TYPE_EDGE_RISING 0>, + <57 257 IRQ_TYPE_EDGE_RISING 0>, + <57 258 IRQ_TYPE_EDGE_RISING 0>, + <57 259 IRQ_TYPE_EDGE_RISING 0>, + <57 260 IRQ_TYPE_EDGE_RISING 0>, + <57 261 IRQ_TYPE_EDGE_RISING 0>; + ... +}; diff --git a/MAINTAINERS b/MAINTAINERS index 82dc44b09a7e..8c7513b02d50 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15023,6 +15023,7 @@ F: Documentation/devicetree/bindings/reset/ti,sci-reset.txt F: Documentation/devicetree/bindings/clock/ti,sci-clk.txt F: drivers/clk/keystone/sci-clk.c F: drivers/reset/reset-ti-sci.c +F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt Texas Instruments ASoC drivers M: Peter Ujfalusi