diff mbox series

[U-Boot,v2,09/11] configs: Remove SF_DUAL_FLASH

Message ID 20181221063836.11429-10-vigneshr@ti.com
State Superseded
Delegated to: Jagannadha Sutradharudu Teki
Headers show
Series SF: Migrate to Linux SPI NOR framework | expand

Commit Message

Raghavendra, Vignesh Dec. 21, 2018, 6:38 a.m. UTC 
SF_DUAL_FLASH claims to enable support for SF_DUAL_STACKED_FLASH and
SF_DUAL_PARALLEL_FLASH. But, in current U-Boot code, grepping for above
enums yield no user and therefore support seems to be incomplete. Remove
these configs so as to avoid confusion.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 configs/topic_miamilite_defconfig           |  1 -
 configs/topic_miamiplus_defconfig           |  1 -
 configs/xilinx_zynqmp_mini_qspi_defconfig   |  1 -
 configs/xilinx_zynqmp_zc1232_revA_defconfig |  1 -
 configs/xilinx_zynqmp_zc1254_revA_defconfig |  1 -
 configs/xilinx_zynqmp_zc1275_revA_defconfig |  1 -
 configs/xilinx_zynqmp_zc1275_revB_defconfig |  1 -
 configs/xilinx_zynqmp_zcu104_revA_defconfig |  1 -
 configs/xilinx_zynqmp_zcu104_revC_defconfig |  1 -
 configs/xilinx_zynqmp_zcu106_revA_defconfig |  1 -
 doc/SPI/README.dual-flash                   | 92 ---------------------
 include/configs/socfpga_stratix10_socdk.h   |  1 -
 12 files changed, 103 deletions(-)
 delete mode 100644 doc/SPI/README.dual-flash

Comments

Jagan Teki Jan. 25, 2019, 2:47 p.m. UTC | #1 
On Fri, Dec 21, 2018 at 12:18 PM Vignesh R <vigneshr@ti.com> wrote:
>
> SF_DUAL_FLASH claims to enable support for SF_DUAL_STACKED_FLASH and
> SF_DUAL_PARALLEL_FLASH. But, in current U-Boot code, grepping for above
> enums yield no user and therefore support seems to be incomplete. Remove
> these configs so as to avoid confusion.

So, with Linux sync. all dual flash code is dropped is it?
Raghavendra, Vignesh Jan. 25, 2019, 3:01 p.m. UTC | #2 
On 25/01/19 8:17 PM, Jagan Teki wrote:
> On Fri, Dec 21, 2018 at 12:18 PM Vignesh R <vigneshr@ti.com> wrote:
>>
>> SF_DUAL_FLASH claims to enable support for SF_DUAL_STACKED_FLASH and
>> SF_DUAL_PARALLEL_FLASH. But, in current U-Boot code, grepping for above
>> enums yield no user and therefore support seems to be incomplete. Remove
>> these configs so as to avoid confusion.
> 
> So, with Linux sync. all dual flash code is dropped is it?
> 

Yes, because Linux does not support dual flash. I did try to add back
dual flash support, but could not find any SPI flash claiming
SF_DUAL_FLASH capability in today's U-Boot code. Therefore, this patch
just drops the CONFIG option.
Dual flash can always be added back to this framework when there is an
actual user of the code in _mainline_ U-Boot.
Jagan Teki Jan. 28, 2019, 6:36 a.m. UTC | #3 
On Fri, Jan 25, 2019 at 8:30 PM Vignesh R <vigneshr@ti.com> wrote:
>
>
>
> On 25/01/19 8:17 PM, Jagan Teki wrote:
> > On Fri, Dec 21, 2018 at 12:18 PM Vignesh R <vigneshr@ti.com> wrote:
> >>
> >> SF_DUAL_FLASH claims to enable support for SF_DUAL_STACKED_FLASH and
> >> SF_DUAL_PARALLEL_FLASH. But, in current U-Boot code, grepping for above
> >> enums yield no user and therefore support seems to be incomplete. Remove
> >> these configs so as to avoid confusion.
> >
> > So, with Linux sync. all dual flash code is dropped is it?
> >
>
> Yes, because Linux does not support dual flash. I did try to add back
> dual flash support, but could not find any SPI flash claiming
> SF_DUAL_FLASH capability in today's U-Boot code. Therefore, this patch
> just drops the CONFIG option.
> Dual flash can always be added back to this framework when there is an
> actual user of the code in _mainline_ U-Boot.

As I said in previous version patches, it is not always to have some
functionalities in Linux and dual flash is useful for bootloader in
Xilinx Zynq IP's.  True that nothing has been done in Linux front and
even we asked about the "plan of work" on this context to Michal and
Siva in previous mails, unfortunately no is responded. On that note
I'm fine with going this change, thanks.
diff mbox series

Patch

diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig
index 4486975f9503..a2ff87a55029 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -41,7 +41,6 @@  CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
-CONFIG_SF_DUAL_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_DEBUG_UART_ZYNQ=y
diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
index ee83f0545bd5..74deff0a19c8 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -40,7 +40,6 @@  CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
-CONFIG_SF_DUAL_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 # CONFIG_NETDEVICES is not set
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index de7bf079551f..1138faffcc39 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -56,7 +56,6 @@  CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
-CONFIG_SF_DUAL_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig
index 7521fc4e34e4..4700956dd2db 100644
--- a/configs/xilinx_zynqmp_zc1232_revA_defconfig
+++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig
@@ -38,7 +38,6 @@  CONFIG_MISC=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
-CONFIG_SF_DUAL_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig
index e0822b931edb..0570414a0532 100644
--- a/configs/xilinx_zynqmp_zc1254_revA_defconfig
+++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig
@@ -38,7 +38,6 @@  CONFIG_MISC=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
-CONFIG_SF_DUAL_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/xilinx_zynqmp_zc1275_revA_defconfig b/configs/xilinx_zynqmp_zc1275_revA_defconfig
index 3afed6973709..7c83f7036814 100644
--- a/configs/xilinx_zynqmp_zc1275_revA_defconfig
+++ b/configs/xilinx_zynqmp_zc1275_revA_defconfig
@@ -38,7 +38,6 @@  CONFIG_MISC=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
-CONFIG_SF_DUAL_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/xilinx_zynqmp_zc1275_revB_defconfig b/configs/xilinx_zynqmp_zc1275_revB_defconfig
index 7e31b1112f8f..e2aade7606bf 100644
--- a/configs/xilinx_zynqmp_zc1275_revB_defconfig
+++ b/configs/xilinx_zynqmp_zc1275_revB_defconfig
@@ -41,7 +41,6 @@  CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
-CONFIG_SF_DUAL_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig
index ff57ca8674e6..b612ce213224 100644
--- a/configs/xilinx_zynqmp_zcu104_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig
@@ -58,7 +58,6 @@  CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
-CONFIG_SF_DUAL_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig
index 0357b1744545..2fb66b2177ab 100644
--- a/configs/xilinx_zynqmp_zcu104_revC_defconfig
+++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig
@@ -59,7 +59,6 @@  CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
-CONFIG_SF_DUAL_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/xilinx_zynqmp_zcu106_revA_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig
index 210c9a347fb2..20e210ec3822 100644
--- a/configs/xilinx_zynqmp_zcu106_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu106_revA_defconfig
@@ -67,7 +67,6 @@  CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
-CONFIG_SF_DUAL_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/doc/SPI/README.dual-flash b/doc/SPI/README.dual-flash
deleted file mode 100644
index 6c88d65dd49f..000000000000
--- a/doc/SPI/README.dual-flash
+++ /dev/null
@@ -1,92 +0,0 @@ 
-SPI/QSPI Dual flash connection modes:
-=====================================
-
-This describes how SPI/QSPI flash memories are connected to a given
-controller in a single chip select line.
-
-Current spi_flash framework supports, single flash memory connected
-to a given controller with single chip select line, but there are some
-hw logics(ex: xilinx zynq qspi) that describes two/dual memories are
-connected with a single chip select line from a controller.
-
-"dual_flash" from include/spi.h describes these types of connection mode
-
-Possible connections:
---------------------
-SF_SINGLE_FLASH:
-       - single spi flash memory connected with single chip select line.
-
-  +------------+             CS         +---------------+
-  |            |----------------------->|               |
-  | Controller |         I0[3:0]        | Flash memory  |
-  | SPI/QSPI   |<======================>| (SPI/QSPI)    |
-  |            |           CLK          |               |
-  |            |----------------------->|               |
-  +------------+                        +---------------+
-
-SF_DUAL_STACKED_FLASH:
-       - dual spi/qspi flash memories are connected with a single chipselect
-         line and these two memories are operating stacked fasion with shared buses.
-       - xilinx zynq qspi controller has implemented this feature [1]
-
-  +------------+        CS             +---------------+
-  |            |---------------------->|               |
-  |            |              I0[3:0]  | Upper Flash   |
-  |            |            +=========>| memory        |
-  |            |            |     CLK  | (SPI/QSPI)    |
-  |            |            |    +---->|               |
-  | Controller |        CS  |    |     +---------------+
-  | SPI/QSPI   |------------|----|---->|               |
-  |            |    I0[3:0] |    |     | Lower Flash   |
-  |            |<===========+====|====>| memory        |
-  |            |          CLK    |     | (SPI/QSPI)    |
-  |            |-----------------+---->|               |
-  +------------+                       +---------------+
-
-       - two memory flash devices should has same hw part attributes (like size,
-         vendor..etc)
-       - Configurations:
-               on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG
-               Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
-               Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory
-       - Operation:
-               accessing memories serially like one after another.
-               by default, if U_PAGE is unset lower memory should accessible,
-               once user wants to access upper memory need to set U_PAGE.
-
-SPI_FLASH_CONN_DUALPARALLEL:
-	- dual spi/qspi flash memories are connected with a single chipselect
-	  line and these two memories are operating parallel with separate buses.
-	- xilinx zynq qspi controller has implemented this feature [1]
-
-  +-------------+           CS		+---------------+
-  |		|---------------------->|		|
-  | 		|        I0[3:0]	| Upper Flash	|
-  | 		|<=====================>| memory	|
-  |		|	   CLK		| (SPI/QSPI)	|
-  |		|---------------------->|		|
-  | Controller	|	    CS		+---------------+
-  | SPI/QSPI	|---------------------->|		|
-  | 		|        I0[3:0]	| Lower Flash	|
-  | 		|<=====================>| memory	|
-  |		|	   CLK		| (SPI/QSPI)	|
-  |		|---------------------->|		|
-  +-------------+			+---------------+
-
-	- two memory flash devices should has same hw part attributes (like size,
-	  vendor..etc)
-	- Configurations:
-		Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG register.
-	- Operation:
-		Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the lower memory
-		and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in the upper memory.
-
-Note: Technically there is only one CS line from the controller, but
-zynq qspi controller has an internal hw logic to enable additional CS
-when controller is configured for dual memories.
-
-[1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
-
---
-Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
-05-01-2014.
diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h
index e190b3d9889d..0b705e6adb80 100644
--- a/include/configs/socfpga_stratix10_socdk.h
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -57,7 +57,6 @@ 
  */
  #ifdef CONFIG_CADENCE_QSPI
 /* Enable it if you want to use dual-stacked mode */
-#undef CONFIG_SF_DUAL_FLASH
 /*#define CONFIG_QSPI_RBF_ADDR		0x720000*/
 
 /* Flash device info */