diff mbox series

[AArch64,SVE] Fix IFN_COND_FMLA movprfx alternative

Message ID 87pntwrwek.fsf@arm.com
State New
Headers show
Series [AArch64,SVE] Fix IFN_COND_FMLA movprfx alternative | expand

Commit Message

Richard Sandiford Dec. 20, 2018, 4:32 p.m. UTC 
This patch fixes a cut-&-pasto in the (match_dup 4) version of
"cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>".  (It's a shame
that there's so much cut-&-paste in these patterns, but it's hard
to avoid without more infrastructure.)

Applied after testing on aarch64-linux-gnu and aarch64_be-elf.

Richard


2018-12-20  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-sve.md (*cond_<optab><mode>_4): Use
	sve_fmla_op rather than sve_fmad_op for the movprfx alternative.

gcc/testsuite/
	* gcc.target/aarch64/sve/fmla_2.c: New test.
	* gcc.target/aarch64/sve/fmla_2_run.c: Likewise
diff mbox series

Patch

Index: gcc/config/aarch64/aarch64-sve.md
===================================================================
--- gcc/config/aarch64/aarch64-sve.md	2018-12-07 15:03:10.893433419 +0000
+++ gcc/config/aarch64/aarch64-sve.md	2018-12-20 16:31:20.946744405 +0000
@@ -3021,7 +3021,7 @@  (define_insn "*cond_<optab><mode>_4"
   "TARGET_SVE"
   "@
    <sve_fmla_op>\t%0.<Vetype>, %1/m, %2.<Vetype>, %3.<Vetype>
-   movprfx\t%0, %4\;<sve_fmad_op>\t%0.<Vetype>, %1/m, %2.<Vetype>, %3.<Vetype>"
+   movprfx\t%0, %4\;<sve_fmla_op>\t%0.<Vetype>, %1/m, %2.<Vetype>, %3.<Vetype>"
   [(set_attr "movprfx" "*,yes")]
 )
 
Index: gcc/testsuite/gcc.target/aarch64/sve/fmla_2.c
===================================================================
--- /dev/null	2018-11-29 13:15:04.463550658 +0000
+++ gcc/testsuite/gcc.target/aarch64/sve/fmla_2.c	2018-12-20 16:31:20.946744405 +0000
@@ -0,0 +1,19 @@ 
+/* { dg-options "-O3" } */
+
+#include <stdint.h>
+
+#define N 55
+
+void __attribute__ ((noipa))
+f (double *restrict a, double *restrict b, double *restrict c,
+   double *restrict d, double *restrict e, int64_t *restrict cond)
+{
+  for (int i = 0; i < N; ++i)
+    {
+      a[i] = cond[i] ? __builtin_fma (c[i], d[i], e[i]) : e[i];
+      b[i] = cond[i] ? __builtin_fma (c[i], e[i], d[i]) : d[i];
+    }
+}
+
+/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
+/* { dg-final { scan-assembler-not {\tfmad\t} } } */
Index: gcc/testsuite/gcc.target/aarch64/sve/fmla_2_run.c
===================================================================
--- /dev/null	2018-11-29 13:15:04.463550658 +0000
+++ gcc/testsuite/gcc.target/aarch64/sve/fmla_2_run.c	2018-12-20 16:31:20.946744405 +0000
@@ -0,0 +1,28 @@ 
+/* { dg-do run { target aarch64_sve_hw } } */
+/* { dg-options "-O3" } */
+
+#include "fmla_2.c"
+
+int __attribute__ ((optimize (1)))
+main (void)
+{
+  double a[N], b[N], c[N], d[N], e[N];
+  int64_t cond[N];
+
+  for (int i = 0; i < N; ++i)
+    {
+      c[i] = i + i % 5;
+      d[i] = i + i % 7;
+      e[i] = i + i % 9;
+      cond[i] = i % 3;
+    }
+
+  f (a, b, c, d, e, cond);
+
+  for (int i = 0; i < N; ++i)
+    if (a[i] != (cond[i] ? __builtin_fma (c[i], d[i], e[i]) : e[i])
+	|| b[i] != (cond[i] ? __builtin_fma (c[i], e[i], d[i]) : d[i]))
+      __builtin_abort ();
+
+  return 0;
+}