| Message ID | 1308858535-17396-1-git-send-email-timur@freescale.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Commit | 7b93eccf2876ba3b1c10dae22ca864a0eb08de4f |
| Delegated to: | Kumar Gala |
| Headers | show |
On Jun 23, 2011, at 2:48 PM, Timur Tabi wrote: > To ensure that the DIU pixel clock will not be set to an invalid value, > clamp the PXCLK divider to the allowed range (2-255). This also acts as > a limiter for the pixel clock. > > Signed-off-by: Timur Tabi <timur@freescale.com> > --- > arch/powerpc/platforms/85xx/p1022_ds.c | 7 ++++++- > 1 files changed, 6 insertions(+), 1 deletions(-) applied to next - K
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c index e083e1f..266b3aa 100644 --- a/arch/powerpc/platforms/85xx/p1022_ds.c +++ b/arch/powerpc/platforms/85xx/p1022_ds.c @@ -195,8 +195,13 @@ void p1022ds_set_pixel_clock(unsigned int pixclock) do_div(temp, pixclock); freq = temp; - /* pixclk is the ratio of the platform clock to the pixel clock */ + /* + * 'pxclk' is the ratio of the platform clock to the pixel clock. + * This number is programmed into the CLKDVDR register, and the valid + * range of values is 2-255. + */ pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq); + pxclk = clamp_t(u32, pxclk, 2, 255); /* Disable the pixel clock, and set it to non-inverted and no delay */ clrbits32(&guts->clkdvdr,
To ensure that the DIU pixel clock will not be set to an invalid value, clamp the PXCLK divider to the allowed range (2-255). This also acts as a limiter for the pixel clock. Signed-off-by: Timur Tabi <timur@freescale.com> --- arch/powerpc/platforms/85xx/p1022_ds.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-)