[nvptx] Generalize bar.sync instruction
Allow the logical barrier operand of nvptx_barsync to be a register, and add a
thread count operand.
Build and reg-tested on x86_64 with nvptx accelerator.
2018-12-17 Tom de Vries <tdevries@suse.de>
* config/nvptx/nvptx.md (nvptx_barsync): Add and handle operand.
* config/nvptx/nvptx.c (nvptx_wsync): Update call to gen_nvptx_barsync.
---
gcc/config/nvptx/nvptx.c | 2 +-
gcc/config/nvptx/nvptx.md | 10 ++++++++--
2 files changed, 9 insertions(+), 3 deletions(-)
@@ -3974,7 +3974,7 @@ nvptx_wpropagate (bool pre_p, bool is_call, basic_block block, rtx_insn *insn)
static rtx
nvptx_wsync (bool after)
{
- return gen_nvptx_barsync (GEN_INT (after));
+ return gen_nvptx_barsync (GEN_INT (after), GEN_INT (0));
}
#if WORKAROUND_PTXJIT_BUG
@@ -1454,10 +1454,16 @@
[(set_attr "atomic" "true")])
(define_insn "nvptx_barsync"
- [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")]
+ [(unspec_volatile [(match_operand:SI 0 "nvptx_nonmemory_operand" "Ri")
+ (match_operand:SI 1 "const_int_operand")]
UNSPECV_BARSYNC)]
""
- "\\tbar.sync\\t%0;"
+ {
+ if (INTVAL (operands[1]) == 0)
+ return "\\tbar.sync\\t%0;";
+ else
+ return "\\tbar.sync\\t%0, %1;";
+ }
[(set_attr "predicable" "false")])
(define_expand "memory_barrier"
[ was: Re: [nvptx] vector length patch series ] On 14-12-18 20:58, Tom de Vries wrote: > 0011-nvptx-Add-thread-count-parm-to-bar.sync.patch Factored out this patch, committed. Thanks, - Tom