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[184.163.105.249]) by smtp.gmail.com with ESMTPSA id y2sm357963qtb.88.2018.12.18.11.07.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 18 Dec 2018 11:07:03 -0800 (PST) From: Vivien Didelot To: netdev@vger.kernel.org Cc: Chris Healy , Vivien Didelot , "John W . Linville" , f.fainelli@gmail.com, andrew@lunn.ch Subject: [PATCH v2 4/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6161 Date: Tue, 18 Dec 2018 14:06:38 -0500 Message-Id: <20181218190641.31883-5-vivien.didelot@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20181218190641.31883-1-vivien.didelot@gmail.com> References: <20181218190641.31883-1-vivien.didelot@gmail.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch adds support for pretty dump the port registers of the 88E6161 and 88E6123 switches, which both share the same datasheet. Signed-off-by: Vivien Didelot --- dsa.c | 164 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 164 insertions(+) diff --git a/dsa.c b/dsa.c index c7e3dd1..ab21d01 100644 --- a/dsa.c +++ b/dsa.c @@ -30,6 +30,168 @@ ((_val) & 0x4000) ? "14 " : "", \ ((_val) & 0x8000) ? "15 " : "") +static void dsa_mv88e6161(int reg, u16 val) +{ + switch (reg) { + case 0: + REG(reg, "Port Status", val); + FIELD("Pause Enabled", "%u", !!(val & 0x8000)); + FIELD("My Pause", "%u", !!(val & 0x4000)); + FIELD("Half-duplex Flow Control", "%u", !!(val & 0x2000)); + FIELD("802.3 PHY Detected", "%u", !!(val & 0x1000)); + FIELD("Link Status", "%s", val & 0x0800 ? "Up" : "Down"); + FIELD("Duplex", "%s", val & 0x0400 ? "Full" : "Half"); + FIELD("Speed", "%s", + (val & 0x0300) == 0x0000 ? "10 Mbps" : + (val & 0x0300) == 0x0100 ? "100 Mbps" : + (val & 0x0300) == 0x0200 ? "1000 Mbps" : + (val & 0x0300) == 0x0300 ? "Reserved" : "?"); + FIELD("Auto-Media Detect Disable", "%u", !!(val & 0x0040)); + FIELD("Transmitter Paused", "%u", !!(val & 0x0020)); + FIELD("Flow Control", "%u", !!(val & 0x0010)); + FIELD("Config Duplex", "%s", val & 0x0008 ? "Full" : "Half"); + FIELD("Config Mode", "0x%x", val & 0x0007); + break; + case 1: + REG(reg, "PCS Control", val); + FIELD("Flow Control's Forced value", "%u", !!(val & 0x0080)); + FIELD("Force Flow Control", "%u", !!(val & 0x0040)); + FIELD("Link's Forced value", "%s", val & 0x0020 ? "Up" : "Down"); + FIELD("Force Link", "%u", !!(val & 0x0010)); + FIELD("Duplex's Forced value", "%s", val & 0x0008 ? "Full" : "Half"); + FIELD("Force Duplex", "%u", !!(val & 0x0004)); + FIELD("Force Speed", "%s", + (val & 0x0003) == 0x0000 ? "10 Mbps" : + (val & 0x0003) == 0x0001 ? "100 Mbps" : + (val & 0x0003) == 0x0002 ? "1000 Mbps" : + (val & 0x0003) == 0x0003 ? "Not forced" : "?"); + break; + case 2: + REG(reg, "Jamming Control", val); + break; + case 3: + REG(reg, "Switch Identifier", val); + break; + case 4: + REG(reg, "Port Control", val); + FIELD("Source Address Filtering controls", "%s", + (val & 0xc000) == 0x0000 ? "Disabled" : + (val & 0xc000) == 0x4000 ? "Drop On Lock" : + (val & 0xc000) == 0x8000 ? "Drop On Unlock" : + (val & 0xc000) == 0xc000 ? "Drop to CPU" : "?"); + FIELD("Egress Mode", "%s", + (val & 0x3000) == 0x0000 ? "Unmodified" : + (val & 0x3000) == 0x1000 ? "Untagged" : + (val & 0x3000) == 0x2000 ? "Tagged" : + (val & 0x3000) == 0x3000 ? "Reserved" : "?"); + FIELD("Ingress & Egress Header Mode", "%u", !!(val & 0x0800)); + FIELD("IGMP and MLD Snooping", "%u", !!(val & 0x0400)); + FIELD("Frame Mode", "%s", + (val & 0x0300) == 0x0000 ? "Normal" : + (val & 0x0300) == 0x0100 ? "DSA" : + (val & 0x0300) == 0x0200 ? "Provider" : + (val & 0x0300) == 0x0300 ? "Ether Type DSA" : "?"); + FIELD("VLAN Tunnel", "%u", !!(val & 0x0080)); + FIELD("TagIfBoth", "%u", !!(val & 0x0040)); + FIELD("Initial Priority assignment", "%s", + (val & 0x0030) == 0x0000 ? "Defaults" : + (val & 0x0030) == 0x0010 ? "Tag Priority" : + (val & 0x0030) == 0x0020 ? "IP Priority" : + (val & 0x0030) == 0x0030 ? "Tag & IP Priority" : "?"); + FIELD("Egress Flooding mode", "%s", + (val & 0x000c) == 0x0000 ? "No unknown DA" : + (val & 0x000c) == 0x0004 ? "No unknown multicast DA" : + (val & 0x000c) == 0x0008 ? "No unknown unicast DA" : + (val & 0x000c) == 0x000c ? "Allow unknown DA" : "?"); + FIELD("Port State", "%s", + (val & 0x0003) == 0x0000 ? "Disabled" : + (val & 0x0003) == 0x0001 ? "Blocking/Listening" : + (val & 0x0003) == 0x0002 ? "Learning" : + (val & 0x0003) == 0x0003 ? "Forwarding" : "?"); + break; + case 5: + REG(reg, "Port Control 1", val); + FIELD("Message Port", "%u", !!(val & 0x8000)); + FIELD("Trunk Port", "%u", !!(val & 0x4000)); + FIELD("Trunk ID", "%u", (val & 0x0f00) >> 8); + FIELD("FID[5:4]", "0x%.2x", (val & 0x0003) << 4); + break; + case 6: + REG(reg, "Port Base VLAN Map (Header)", val); + FIELD("FID[3:0]", "0x%.2x", (val & 0xf000) >> 12); + FIELD_BITMAP("VLANTable", val & 0x003f); + break; + case 7: + REG(reg, "Default VLAN ID & Priority", val); + FIELD("Default Priority", "0x%x", (val & 0xe000) >> 13); + FIELD("Force to use Default VID", "%u", !!(val & 0x1000)); + FIELD("Default VLAN Identifier", "%u", val & 0x0fff); + break; + case 8: + REG(reg, "Port Control 2", val); + FIELD("Force good FCS in the frame", "%u", !!(val & 0x8000)); + FIELD("Jumbo Mode", "%s", + (val & 0x3000) == 0x0000 ? "1522" : + (val & 0x3000) == 0x1000 ? "2048" : + (val & 0x3000) == 0x2000 ? "10240" : + (val & 0x3000) == 0x3000 ? "Reserved" : "?"); + FIELD("802.1QMode", "%s", + (val & 0x0c00) == 0x0000 ? "Disabled" : + (val & 0x0c00) == 0x0400 ? "Fallback" : + (val & 0x0c00) == 0x0800 ? "Check" : + (val & 0x0c00) == 0x0c00 ? "Secure" : "?"); + FIELD("Discard Tagged Frames", "%u", !!(val & 0x0200)); + FIELD("Discard Untagged Frames", "%u", !!(val & 0x0100)); + FIELD("Map using DA hits", "%u", !!(val & 0x0080)); + FIELD("ARP Mirror enable", "%u", !!(val & 0x0040)); + FIELD("Egress Monitor Source Port", "%u", !!(val & 0x0020)); + FIELD("Ingress Monitor Source Port", "%u", !!(val & 0x0010)); + break; + case 9: + REG(reg, "Egress Rate Control", val); + break; + case 10: + REG(reg, "Egress Rate Control 2", val); + break; + case 11: + REG(reg, "Port Association Vector", val); + break; + case 12: + REG(reg, "Port ATU Control", val); + break; + case 13: + REG(reg, "Priority Override", val); + break; + case 15: + REG(reg, "PortEType", val); + break; + case 16: + REG(reg, "InDiscardsLo Frame Counter", val); + break; + case 17: + REG(reg, "InDiscardsHi Frame Counter", val); + break; + case 18: + REG(reg, "InFiltered Frame Counter", val); + break; + case 19: + REG(reg, "OutFiltered Frame Counter", val); + break; + case 24: + REG(reg, "Tag Remap 0-3", val); + break; + case 25: + REG(reg, "Tag Remap 4-7", val); + break; + case 27: + REG(reg, "Queue Counters", val); + break; + default: + REG(reg, "Reserved", val); + break; + } +} + static void dsa_mv88e6185(int reg, u16 val) { switch (reg) { @@ -97,6 +259,8 @@ struct dsa_mv88e6xxx_switch { }; static const struct dsa_mv88e6xxx_switch dsa_mv88e6xxx_switches[] = { + { .id = 0x1210, .name = "88E6123 ", .dump = dsa_mv88e6161 }, + { .id = 0x1610, .name = "88E6161 ", .dump = dsa_mv88e6161 }, { .id = 0x1a70, .name = "88E6185 ", .dump = dsa_mv88e6185 }, };