From patchwork Tue Dec 18 09:12:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1015186 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="WkYoorHB"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43Jskq6RFWz9sBZ for ; Tue, 18 Dec 2018 20:13:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726447AbeLRJNX (ORCPT ); Tue, 18 Dec 2018 04:13:23 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:13129 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726406AbeLRJNX (ORCPT ); Tue, 18 Dec 2018 04:13:23 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 18 Dec 2018 01:13:14 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 18 Dec 2018 01:13:22 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 18 Dec 2018 01:13:22 -0800 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 18 Dec 2018 09:13:22 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 18 Dec 2018 09:13:21 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 18 Dec 2018 09:13:21 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 18 Dec 2018 01:13:21 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo Subject: [PATCH V3 16/20] arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support Date: Tue, 18 Dec 2018 17:12:28 +0800 Message-ID: <20181218091232.23532-17-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20181218091232.23532-1-josephl@nvidia.com> References: <20181218091232.23532-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1545124394; bh=szLdxrv4BLINqeEVR7DXGll16Bew+UCxZyKAvX8uqq4=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=WkYoorHBjZicJHd1isYVolC+aWWWuaF6wJTWrBOhMRQGvjcVm/S+F1hAywRMSqoZM NurB6rHBDgWYUtU0TRP0DQzTHAahr8j9/FmsyfK2Qs6/B5sHUFuUCMxwoWWENw+K3/ ul+B4ebMpsAQYjn5i8lRA4jnktBm4bRaruSTR+uTl+KCq3v1veCyOriFG+F8SrAeky jDgYUkikoqjgjABHxWk1OggJRj9bmWMahbvc4HAvCvzw+XWOwCaMWkTdJXt/lWED62 tvygLam1yuelu+0gCtEnHm7DC2O6LkAMW2pkf8+XQP8HW8TmnRyz35bNKVrhOVlacu qMrsDxrdQLfSQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add pinmux for PWM-based DFLL support. Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- *V3: - no change *V2: - add ack tag --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index a96e6ee70c21..0ee25a5188f8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1278,6 +1278,20 @@ nvidia,open-drain = ; }; }; + + dvfs_pwm_active_state: dvfs_pwm_active { + dvfs_pwm_pbb1 { + nvidia,pins = "dvfs_pwm_pbb1"; + nvidia,tristate = ; + }; + }; + + dvfs_pwm_inactive_state: dvfs_pwm_inactive { + dvfs_pwm_pbb1 { + nvidia,pins = "dvfs_pwm_pbb1"; + nvidia,tristate = ; + }; + }; }; pwm@7000a000 {