From patchwork Tue Jun 21 12:55:11 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jamie Iles X-Patchwork-Id: 101283 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 45FB8B6F72 for ; Tue, 21 Jun 2011 22:58:17 +1000 (EST) Received: from localhost ([::1]:52271 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QZ0Wz-0006lu-CU for incoming@patchwork.ozlabs.org; Tue, 21 Jun 2011 08:58:13 -0400 Received: from eggs.gnu.org ([140.186.70.92]:51165) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QZ0UK-0006l7-3d for qemu-devel@nongnu.org; Tue, 21 Jun 2011 08:55:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QZ0UI-0003FJ-4j for qemu-devel@nongnu.org; Tue, 21 Jun 2011 08:55:27 -0400 Received: from mail-ww0-f41.google.com ([74.125.82.41]:40379) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QZ0UH-0003F2-Hy for qemu-devel@nongnu.org; Tue, 21 Jun 2011 08:55:25 -0400 Received: by wwi18 with SMTP id 18so218657wwi.4 for ; Tue, 21 Jun 2011 05:55:24 -0700 (PDT) Received: by 10.227.154.3 with SMTP id m3mr2730103wbw.31.1308660923797; Tue, 21 Jun 2011 05:55:23 -0700 (PDT) Received: from localhost (gw-ba1.picochip.com [94.175.234.108]) by mx.google.com with ESMTPS id ei4sm3988555wbb.9.2011.06.21.05.55.22 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 21 Jun 2011 05:55:22 -0700 (PDT) From: Jamie Iles To: qemu-devel@nongnu.org Date: Tue, 21 Jun 2011 13:55:11 +0100 Message-Id: <1308660911-9840-1-git-send-email-jamie.iles@picochip.com> X-Mailer: git-send-email 1.7.4.1 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 74.125.82.41 Cc: Jamie Iles , Paul Brook , Aurelien Jarno Subject: [Qemu-devel] [PATCH] target-arm: support for ARM1176JZ-s cores X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add support for the ARM1176JZ-s cores. The ARM1176JZ-s is a v6K core but uses the v7 VMSA for remapping and access permissions and there is no way to identify these VMSA extensions from the cpuid feature registers. Cc: Paul Brook Cc: Aurelien Jarno Signed-off-by: Jamie Iles --- target-arm/cpu.h | 1 + target-arm/helper.c | 23 ++++++++++++++++++++++- 2 files changed, 23 insertions(+), 1 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 01f5b57..8708f9e 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -414,6 +414,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define ARM_CPUID_PXA270_C5 0x69054117 #define ARM_CPUID_ARM1136 0x4117b363 #define ARM_CPUID_ARM1136_R2 0x4107b362 +#define ARM_CPUID_ARM1176 0x410fb767 #define ARM_CPUID_ARM11MPCORE 0x410fb022 #define ARM_CPUID_CORTEXA8 0x410fc080 #define ARM_CPUID_CORTEXA9 0x410fc090 diff --git a/target-arm/helper.c b/target-arm/helper.c index 1208416..63df576 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -36,6 +36,12 @@ static uint32_t arm1136_cp15_c0_c1[8] = static uint32_t arm1136_cp15_c0_c2[8] = { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 }; +static uint32_t arm1176_cp15_c0_c1[8] = +{ 0x111, 0x11, 0x33, 0x01130003, 0x01130003, 0x10030302, 0x01222100, 0 }; + +static uint32_t arm1176_cp15_c0_c2[8] = +{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 }; + static uint32_t cpu_arm_find_by_name(const char *name); static inline void set_feature(CPUARMState *env, int feature) @@ -86,6 +92,17 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00050078; break; + case ARM_CPUID_ARM1176: + set_feature(env, ARM_FEATURE_V4T); + set_feature(env, ARM_FEATURE_V5); + set_feature(env, ARM_FEATURE_V6); + set_feature(env, ARM_FEATURE_V6K); + set_feature(env, ARM_FEATURE_AUXCR); + memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t)); + memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t)); + env->cp15.c0_cachetype = 0x1dd20d2; + env->cp15.c1_sys = 0x00050078; + break; case ARM_CPUID_ARM11MPCORE: set_feature(env, ARM_FEATURE_V4T); set_feature(env, ARM_FEATURE_V5); @@ -377,6 +394,7 @@ static const struct arm_cpu_t arm_cpu_names[] = { { ARM_CPUID_ARM1026, "arm1026"}, { ARM_CPUID_ARM1136, "arm1136"}, { ARM_CPUID_ARM1136_R2, "arm1136-r2"}, + { ARM_CPUID_ARM1176, "arm1176"}, { ARM_CPUID_ARM11MPCORE, "arm11mpcore"}, { ARM_CPUID_CORTEXM3, "cortex-m3"}, { ARM_CPUID_CORTEXA8, "cortex-a8"}, @@ -945,7 +963,9 @@ static inline int check_ap(CPUState *env, int ap, int domain, int access_type, case 6: return prot_ro; case 7: - if (!arm_feature (env, ARM_FEATURE_V7)) + /* ARM1176 uses VMSAv7 remapping and access flag. */ + if (!arm_feature (env, ARM_FEATURE_V7) && + ARM_CPUID(env) != ARM_CPUID_ARM1176) return 0; return prot_ro; default: @@ -1770,6 +1790,7 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) return 1; case ARM_CPUID_ARM1136: case ARM_CPUID_ARM1136_R2: + case ARM_CPUID_ARM1176: return 7; case ARM_CPUID_ARM11MPCORE: return 1;