Message ID | 20181213093438.29621-17-josephl@nvidia.com |
---|---|
State | Changes Requested |
Headers | show
Return-Path: <linux-tegra-owner@vger.kernel.org> X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=<UNKNOWN>) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="pJ4Wuf5n"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43FpSd6X7Dz9s6w for <incoming@patchwork.ozlabs.org>; Thu, 13 Dec 2018 20:35:29 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728008AbeLMJf2 (ORCPT <rfc822;incoming@patchwork.ozlabs.org>); Thu, 13 Dec 2018 04:35:28 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:18415 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727754AbeLMJf2 (ORCPT <rfc822;linux-tegra@vger.kernel.org>); Thu, 13 Dec 2018 04:35:28 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id <B5c1227dc0001>; Thu, 13 Dec 2018 01:35:24 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 13 Dec 2018 01:35:27 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 13 Dec 2018 01:35:27 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 13 Dec 2018 09:35:27 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 13 Dec 2018 09:35:27 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id <B5c1227de0000>; Thu, 13 Dec 2018 01:35:27 -0800 From: Joseph Lo <josephl@nvidia.com> To: Thierry Reding <thierry.reding@gmail.com>, Peter De Schrijver <pdeschrijver@nvidia.com>, Jonathan Hunter <jonathanh@nvidia.com> CC: <linux-arm-kernel@lists.infradead.org>, <linux-tegra@vger.kernel.org>, <linux-clk@vger.kernel.org>, Joseph Lo <josephl@nvidia.com> Subject: [PATCH V2 16/21] arm64: dts: tegra210: add CPU clocks Date: Thu, 13 Dec 2018 17:34:33 +0800 Message-ID: <20181213093438.29621-17-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213093438.29621-1-josephl@nvidia.com> References: <20181213093438.29621-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1544693725; bh=IOFyNrXme1XvpLzaM5Q74BOZMpiiK/bO+bMyzkSHmOU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=pJ4Wuf5n4JLXZ5FS3z1CRxRMN39/4wNrCCJytdjx8xHjj6js7PgT8yG9+0F6YQ7PM s/fTgUdEjAKtK8w6jORFqB6xJ+j7LersCdXBXYXc3ZpB3Dd236o73cfSF0315/Wrgi 1I7gf8XkRPTJ2PqFHvY0M4Ocw55TB9EUe0v4uBW08CeQxoxVHtqdr/1G74nYhT8K/m AMmPbmK7EYQW8D8aSObqnnoZK9ruC52ndsNQvil9VQBHXk7E0esZchan8s/aVzVjaq dAhRVB7yAu5GKtNOyz6zy+8PGKHCwASFu9Fc0Lp+Avd6RgRmd0M/Hx8Ozo0hTbxqac pxGTd0kY7hyfQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: <linux-tegra.vger.kernel.org> X-Mailing-List: linux-tegra@vger.kernel.org |
Series |
Tegra210 DFLL support
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expand
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diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index a6db62157442..e2baf52fe1af 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1304,6 +1304,12 @@ device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0>; + clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, + <&tegra_car TEGRA210_CLK_PLL_X>, + <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, + <&dfll>; + clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; + clock-latency = <300000>; }; cpu@1 {