Patchwork [AVR] : Fix PR33049 (implement extzv)

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Submitter Georg-Johann Lay
Date June 21, 2011, 9:45 a.m.
Message ID <4E006828.2060404@gjlay.de>
Download mbox | patch
Permalink /patch/101268/
State New
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Comments

Georg-Johann Lay - June 21, 2011, 9:45 a.m.
Denis Chertykov schrieb:
> 2011/6/20 Georg-Johann Lay <avr@gjlay.de>:
>> This is an optimization patch that implements extzv for 1-bit extracts.
> 
> 
>> +(define_insn_and_split "*extzv"
>> +  [(set (match_operand:QI 0 "register_operand"                    "=*d,*d,*d,r")
>> +        (zero_extract:QI (match_operand:QI 1 "register_operand"     "0,r,0,r")
>> +                         (const_int 1)
>> +                         (match_operand:QI 2 "const_0_to_7_operand" "L,L,P,n")))]
>> +  ""
>> +  "@
>> +	andi %0,1
>> +	mov %0,%1\;andi %0,1
>> +	lsr %0\;andi %0,1
>> +	bst %1,%2\;clr %0\;bld %0,0"
> 
> Why you have a second constraint alternative (*d,r,L) ?
> IMHO it's unnecessary.

The second alternative takes 2 instructions/ticks whereas the last
alternative -- which would be taken without alternative 2 -- takes 3
instructions/ticks.  As because of '*' there is no preference on
register class, allocator just sees "r,r,n" and if the output register
happens to end up in 'd' shorter sequences are possible in some cases.
But there is no pressure being put to get such an alternative; in
particular, allocator does not see "d,0,L" and does not emit a move to
reload input.

>> +   && REGNO (operands[0]) >= 16"
> 
> It's not a good practice to refer to register as number.
> 
> Denis.

Ok.  d_register_operand or satisfies_constraint_d would do.  But I
preferred to introduce a new constraint for 4 and avoid splitting
*extzv altogether to keep it simple.  Complexity of splitting is not a
real advantage over writing things down directly.

As avr is running out of constraint letters, I started 3-letter
constraints 'Y**' in the style of bfin.  Would be nice if 'K' was not
already occupied or could be deprecated (is'n not really useful in
inline asm)...

The split patterns just need one alternative, so there is just this
one 'r,r,n' alternative now.

Again, tested without regression.

Johann

	PR target/33049
	* config/avr/avr.md (extzv): New expander.
	(*extzv): New insn.
	(*extzv.qihi1, *extzv.qihi2): New insn-and-split.
	* config/avr/constraints.md (Y04): New constraint.
	* doc/md.texi (Machine Constraints): Document it.
Denis Chertykov - June 21, 2011, 12:04 p.m.
2011/6/21 Georg-Johann Lay <avr@gjlay.de>:
> Denis Chertykov schrieb:
>> 2011/6/20 Georg-Johann Lay <avr@gjlay.de>:
>>> This is an optimization patch that implements extzv for 1-bit extracts.
>>
>>
>>> +(define_insn_and_split "*extzv"
>>> +  [(set (match_operand:QI 0 "register_operand"                    "=*d,*d,*d,r")
>>> +        (zero_extract:QI (match_operand:QI 1 "register_operand"     "0,r,0,r")
>>> +                         (const_int 1)
>>> +                         (match_operand:QI 2 "const_0_to_7_operand" "L,L,P,n")))]
>>> +  ""
>>> +  "@
>>> +    andi %0,1
>>> +    mov %0,%1\;andi %0,1
>>> +    lsr %0\;andi %0,1
>>> +    bst %1,%2\;clr %0\;bld %0,0"
>>
>> Why you have a second constraint alternative (*d,r,L) ?
>> IMHO it's unnecessary.
>
> The second alternative takes 2 instructions/ticks whereas the last
> alternative -- which would be taken without alternative 2 -- takes 3
> instructions/ticks.  As because of '*' there is no preference on
> register class, allocator just sees "r,r,n" and if the output register
> happens to end up in 'd' shorter sequences are possible in some cases.
> But there is no pressure being put to get such an alternative; in
> particular, allocator does not see "d,0,L" and does not emit a move to
> reload input.

Ok.

>
>>> +   && REGNO (operands[0]) >= 16"
>>
>> It's not a good practice to refer to register as number.
>>
>> Denis.
>
> Ok.  d_register_operand or satisfies_constraint_d would do.  But I
> preferred to introduce a new constraint for 4 and avoid splitting
> *extzv altogether to keep it simple.  Complexity of splitting is not a
> real advantage over writing things down directly.
>
> As avr is running out of constraint letters, I started 3-letter
> constraints 'Y**' in the style of bfin.  Would be nice if 'K' was not
> already occupied or could be deprecated (is'n not really useful in
> inline asm)...

Better to choose starting letter different to pointer register names X,Y,Z.
May be better to use underscore '_' ?


Denis.
Georg-Johann Lay - June 21, 2011, 12:16 p.m.
Denis Chertykov schrieb:
> 2011/6/21 Georg-Johann Lay:

>> Ok.  d_register_operand or satisfies_constraint_d would do.  But I
>> preferred to introduce a new constraint for 4 and avoid splitting
>> *extzv altogether to keep it simple.  Complexity of splitting is not a
>> real advantage over writing things down directly.
>>
>> As avr is running out of constraint letters, I started 3-letter
>> constraints 'Y**' in the style of bfin.  Would be nice if 'K' was not
>> already occupied or could be deprecated (is'n not really useful in
>> inline asm)...
> 
> Better to choose starting letter different to pointer register names X,Y,Z.
> May be better to use underscore '_' ?
> 
> Denis.

My preference would be to change 'K' to 'K02' and thus deprecate 'K'.

Other letters are 'A', 'B', 'C', D', 'R', 'S', 'T', 'U', 'W', 'Z'.
I do not like '_' as constraint.
'R' might be needed in the future for more register constraints (r24,
r24-r25, r22-25, ...) and 'R' is a nice prefix.
'C' looks appealing for constant.

Johann
Denis Chertykov - June 21, 2011, 12:38 p.m.
2011/6/21 Georg-Johann Lay <avr@gjlay.de>:
> Denis Chertykov schrieb:
>> 2011/6/21 Georg-Johann Lay:
>
>>> Ok.  d_register_operand or satisfies_constraint_d would do.  But I
>>> preferred to introduce a new constraint for 4 and avoid splitting
>>> *extzv altogether to keep it simple.  Complexity of splitting is not a
>>> real advantage over writing things down directly.
>>>
>>> As avr is running out of constraint letters, I started 3-letter
>>> constraints 'Y**' in the style of bfin.  Would be nice if 'K' was not
>>> already occupied or could be deprecated (is'n not really useful in
>>> inline asm)...
>>
>> Better to choose starting letter different to pointer register names X,Y,Z.
>> May be better to use underscore '_' ?
>>
>> Denis.
>
> My preference would be to change 'K' to 'K02' and thus deprecate 'K'.
>
> Other letters are 'A', 'B', 'C', D', 'R', 'S', 'T', 'U', 'W', 'Z'.
> I do not like '_' as constraint.
> 'R' might be needed in the future for more register constraints (r24,
> r24-r25, r22-25, ...) and 'R' is a nice prefix.
> 'C' looks appealing for constant.

I'm vote for 'C'.

Denis.

Patch

Index: doc/md.texi
===================================================================
--- doc/md.texi	(revision 175201)
+++ doc/md.texi	(working copy)
@@ -1773,6 +1773,9 @@  Integer constant in the range @minus{}6
 
 @item Q
 A memory address based on Y or Z pointer with displacement.
+
+@item Y04
+Constant integer 4
 @end table
 
 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
Index: config/avr/constraints.md
===================================================================
--- config/avr/constraints.md	(revision 175201)
+++ config/avr/constraints.md	(working copy)
@@ -107,3 +107,8 @@  (define_memory_constraint "Q"
   "A memory address based on Y or Z pointer with displacement."
   (and (match_code "mem")
        (match_test "extra_constraint_Q (op)")))
+
+(define_constraint "Y04"
+  "Constant integer 4."
+  (and (match_code "const_int")
+       (match_test "ival == 4")))
Index: config/avr/avr.md
===================================================================
--- config/avr/avr.md	(revision 175201)
+++ config/avr/avr.md	(working copy)
@@ -3540,3 +3540,65 @@  (define_insn_and_split "*ior<mode>qi.byt
     int byteno = INTVAL(operands[2]) / BITS_PER_UNIT;
     operands[4] = simplify_gen_subreg (QImode, operands[0], <MODE>mode, byteno);
   })
+
+(define_expand "extzv"
+  [(set (match_operand:QI 0 "register_operand" "")
+        (zero_extract:QI (match_operand:QI 1 "register_operand"  "")
+                         (match_operand:QI 2 "const1_operand" "")
+                         (match_operand:QI 3 "const_0_to_7_operand" "")))]
+  ""
+  "")
+
+(define_insn "*extzv"
+  [(set (match_operand:QI 0 "register_operand"                   "=*d,*d,*d,*d,r")
+        (zero_extract:QI (match_operand:QI 1 "register_operand"     "0,r,0,0,r")
+                         (const_int 1)
+                         (match_operand:QI 2 "const_0_to_7_operand" "L,L,P,Y04,n")))]
+  ""
+  "@
+	andi %0,1
+	mov %0,%1\;andi %0,1
+	lsr %0\;andi %0,1
+        swap %0\;andi %0,1
+	bst %1,%2\;clr %0\;bld %0,0"
+  [(set_attr "length" "1,2,2,2,3")
+   (set_attr "cc" "set_zn,set_zn,set_zn,set_zn,clobber")])
+
+(define_insn_and_split "*extzv.qihi1"
+  [(set (match_operand:HI 0 "register_operand"                     "=r")
+        (zero_extract:HI (match_operand:QI 1 "register_operand"     "r")
+                         (const_int 1)
+                         (match_operand:QI 2 "const_0_to_7_operand" "n")))]
+  ""
+  "#"
+  ""
+  [(set (match_dup 3)
+        (zero_extract:QI (match_dup 1)
+                         (const_int 1)
+                         (match_dup 2)))
+   (set (match_dup 4)
+        (const_int 0))]
+  {
+    operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 0);
+    operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
+  })
+
+(define_insn_and_split "*extzv.qihi2"
+  [(set (match_operand:HI 0 "register_operand"                      "=r")
+        (zero_extend:HI 
+         (zero_extract:QI (match_operand:QI 1 "register_operand"     "r")
+                          (const_int 1)
+                          (match_operand:QI 2 "const_0_to_7_operand" "n"))))]
+  ""
+  "#"
+  ""
+  [(set (match_dup 3)
+        (zero_extract:QI (match_dup 1)
+                         (const_int 1)
+                         (match_dup 2)))
+   (set (match_dup 4)
+        (const_int 0))]
+  {
+    operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 0);
+    operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
+  })