[U-Boot,v5,20/25] riscv: Fix context restore before returning from trap handler

From: Bin Meng <bmeng.cn@gmail.com>
To: Rick Chen <rick@andestech.com>, Simon Glass <sjg@chromium.org>,
	Lukas Auer <lukas.auer@aisec.fraunhofer.de>,
	Anup Patel <anup@brainfault.org>,
	U-Boot Mailing List <u-boot@lists.denx.de>
Date: Wed, 12 Dec 2018 06:12:42 -0800
Message-Id: <1544623967-30010-21-git-send-email-bmeng.cn@gmail.com>
In-Reply-To: <1544623967-30010-1-git-send-email-bmeng.cn@gmail.com>
References: <1544623967-30010-1-git-send-email-bmeng.cn@gmail.com>
Subject: [U-Boot] [PATCH v5 20/25] riscv: Fix context restore before
	returning from trap handler
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Message ID	1544623967-30010-21-git-send-email-bmeng.cn@gmail.com
State	Accepted
Delegated to:	Andes
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Bin Meng <bmeng.cn@gmail.com> To: Rick Chen <rick@andestech.com>, Simon Glass <sjg@chromium.org>, Lukas Auer <lukas.auer@aisec.fraunhofer.de>, Anup Patel <anup@brainfault.org>, U-Boot Mailing List <u-boot@lists.denx.de> Date: Wed, 12 Dec 2018 06:12:42 -0800 Message-Id: <1544623967-30010-21-git-send-email-bmeng.cn@gmail.com> In-Reply-To: <1544623967-30010-1-git-send-email-bmeng.cn@gmail.com> References: <1544623967-30010-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v5 20/25] riscv: Fix context restore before returning from trap handler Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	riscv: Adding RISC-V CPU and timer driver \| expand [U-Boot,v5,00/25] riscv: Adding RISC-V CPU and timer driver [U-Boot,v5,01/25] riscv: add Kconfig entries for the code model [U-Boot,v5,02/25] dm: cpu: Add timebase frequency to the platdata [U-Boot,v5,03/25] riscv: qemu: Create a simple-bus driver for the soc node [U-Boot,v5,04/25] cpu: Add a RISC-V CPU driver [U-Boot,v5,05/25] timer: Add generic driver for RISC-V privileged architecture defined timer [U-Boot,v5,06/25] riscv: ax25: Hide the ax25-specific Kconfig option [U-Boot,v5,07/25] riscv: Introduce a Kconfig option for machine mode [U-Boot,v5,08/25] riscv: Add a SYSCON driver for SiFive's Core Local Interruptor [U-Boot,v5,09/25] riscv: Implement riscv_get_time() API using rdtime instruction [U-Boot,v5,10/25] riscv: qemu: Add platform-specific Kconfig options [U-Boot,v5,11/25] riscv: Enlarge the default SYS_MALLOC_F_LEN [U-Boot,v5,12/25] riscv: Probe cpus during boot [U-Boot,v5,13/25] riscv: Remove non-DM version of print_cpuinfo() [U-Boot,v5,14/25] riscv: Add CSR numbers [U-Boot,v5,15/25] riscv: Add exception codes for xcause register [U-Boot,v5,16/25] riscv: Update supports_extension() to use desc from cpu driver [U-Boot,v5,17/25] riscv: Add indirect stringification to csr_xxx ops [U-Boot,v5,18/25] riscv: Do some basic architecture level cpu initialization [U-Boot,v5,19/25] riscv: Move trap handler codes to mtrap.S [U-Boot,v5,20/25] riscv: Fix context restore before returning from trap handler [U-Boot,v5,21/25] riscv: Return to previous privilege level after trap handling [U-Boot,v5,22/25] riscv: Adjust the _exit_trap() position to come before handle_trap() [U-Boot,v5,23/25] riscv: Save boot hart id to the global data [U-Boot,v5,24/25] riscv: bootm: Change to use boot_hart from global data [U-Boot,v5,25/25] riscv: Remove ae350.dts

[U-Boot,v5,20/25] riscv: Fix context restore before returning from trap handler

Commit Message

Patch