| Message ID | 1544285898-24255-1-git-send-email-andrew@lunn.ch |
|---|---|
| State | New |
| Headers | show |
| Series | gpio: tqmx86: Add GPIO driver for this IO controller | expand |
Hi Andrew! Thanks for your patch! On Sat, Dec 8, 2018 at 5:18 PM Andrew Lunn <andrew@lunn.ch> wrote: > Some TQ-Systems ComExpress modules contain an IO controller with 8 > GPIO lines. > > Signed-off-by: Andrew Lunn <andrew@lunn.ch> > +config GPIO_TQMX86 > + tristate "TQ-Systems QTMX86 GPIO" > + depends on MFD_TQMX86 > + select GENERIC_IRQ_CHIP I'd say probably remove that and add: select GPIO_GENERIC select GPIOLIB_IRQCHIP Becuase I think this driver can use these two abstractions quite nicely. It will diet the driver down to a very few lines of code, which is nice. I am almost 100% sure that you can use GPIO_GENERIC and 80% sure you can use GPIOLIB_IRQCHIP. > +#include <linux/gpio.h> Just #include <linux/gpio/driver.h> these days. > +#include <linux/irq.h> > +#include <linux/irqdomain.h> > +#include <linux/interrupt.h> With the GPIOLIB_IRQCHIP you don't need these. > +#define TQMX86_NGPIO 8 > +#define TQMX86_DIR_MASK 0xf0 /* 0-3 - output, 4-7 - input */ > +#define TQMX86_GPIODD 0 /* GPIO Data Direction Register */ > +#define TQMX86_GPIOD 1 /* GPIO Data Register */ > +#define TQMX86_GPIIC 3 /* GPI Interrupt Configuration Register */ > +#define TQMX86_GPIIS 4 /* GPI Interrupt Status Register */ This looks like a very straight-forward MMIO GPIO, which means I think you can just use GPIO_GENERIC. Look at one of the examples, like drivers/gpio/gpio-ftgpio010.c that show how to get a compact driver with these. As a bonus, using the generic driver gives you implementations of .get_multiple() and .set_multiple() for free. > +struct tqmx86_gpio_data { > + struct gpio_chip chip; > + void __iomem *io_base; > + struct irq_domain *domain; > + int irq; No need for storing IRQs and irq domains if you use GPIOLIB_IRQCHIP. > + spinlock_t spinlock; And GPIO_MMIO contains its own spinlock. > + u8 irq_type[4]; > + int irqs[4]; /* mapped irqs */ This will likely be handled too. > +static u8 tqmx86_gpio_read(struct tqmx86_gpio_data *gd, unsigned int reg) > +static void tqmx86_gpio_write(struct tqmx86_gpio_data *gd, u8 val, > + unsigned int reg) > +static int tqmx86_gpio_get(struct gpio_chip *chip, unsigned int offset) > +static void tqmx86_gpio_set(struct gpio_chip *chip, unsigned int offset, > + int value) > +static int tqmx86_gpio_direction_input(struct gpio_chip *chip, > + unsigned int offset) > +static int tqmx86_gpio_direction_output(struct gpio_chip *chip, > + unsigned int offset, > + int value) > +static int tqmx86_gpio_get_direction(struct gpio_chip *chip, > + unsigned int offset) All of these will be assigned to default implementations after you call bgpio_init() on your gpiolib so they just go away. > +static int tqmx86_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) (...) > + if (offset < 4 || offset > 7) > + return -EINVAL; > + ret = irq_create_mapping(gpio->domain, offset - 4); > + if (ret > 0) > + gpio->irqs[offset - 4] = ret; This "offset of 4" is something I don't quite get and would stop you from using GPIOLIB_IRQCHIP. The gpiolib irqchip implementation sort of assumes offset 0..n > +static void tqmx86_gpio_irq_noop(struct irq_data *data) > +{ > +} > + > +static void tqmx86_gpio_irq_mask(struct irq_data *data) > +{ > + struct tqmx86_gpio_data *gpio = data->domain->host_data; > + unsigned long flags, irq_mask = data->mask; > + int i; > + u8 gpiic, mask = 0; > + > + for_each_set_bit(i, &irq_mask, 4) > + mask |= 3 << (2 * i); This looks strange, can we have some comment explaining what happens here? Something like two bits per IRQ I get it, but how are the bits arranged in the register? And why does it start on 4? > + if (mask) { > + spin_lock_irqsave(&gpio->spinlock, flags); > + gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); > + gpiic &= ~mask; > + tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC); > + spin_unlock_irqrestore(&gpio->spinlock, flags); > + } So you can still use your own irqchip with GPIO_GENERIC, just use spin_lock(&chip->bgpio_lock); that comes with GPIO_GENERIC. > +static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) > +{ > + struct tqmx86_gpio_data *gpio = data->domain->host_data; > + unsigned int edge_type = type & IRQF_TRIGGER_MASK; > + unsigned int offset = data->hwirq * 2; /* 2 bits per line */ > + unsigned long flags; > + u8 new_type, gpiic; > + > + if (edge_type == IRQ_TYPE_EDGE_RISING) > + new_type = TQMX86_GPII_RISING; > + else if (edge_type == IRQ_TYPE_EDGE_FALLING) > + new_type = TQMX86_GPII_FALLING; > + else > + return -EINVAL; /* not supported */ > + > + gpio->irq_type[offset] = new_type; So it doesn't support both egdes at the same time? Since they appear to be two different bits it seems like it can? > + spin_lock_irqsave(&gpio->spinlock, flags); > + gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); > + gpiic &= ~(3 << offset); > + gpiic |= new_type << offset; > + tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC); > + spin_unlock_irqrestore(&gpio->spinlock, flags); > + /* TODO: find offset, set GPIIC */ > + > + irqd_set_trigger_type(data, type); This is why you need irq_noop, because setting it to rising/falling edge will call the .ack callback. Maybe it's fine like this but then add a comment about this to the noop callback. > +static irqreturn_t tqmx86_gpio_irq_cascade(int irq, void *data) I usually just call it irq_handler or something for familiarity. > +{ > + struct tqmx86_gpio_data *gpio = data; > + u8 irq_status = tqmx86_gpio_read(gpio, TQMX86_GPIIS); > + int i; > + unsigned long irq_bits; > + > + if (!irq_status) > + return IRQ_HANDLED; > + > + tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS); > + > + irq_bits = irq_status; > + for_each_set_bit(i, &irq_bits, 4) > + generic_handle_irq(irq_find_mapping(gpio->domain, i)); > + > + return IRQ_HANDLED; > +} So if you can use GPIOLIB_IRQCHIP you just use chained_irq_enter()/exit() in this handler before calling generic_handle_irq() > + chip = &gpio->chip; > + chip->label = "gpio-tqmx86"; > + chip->owner = THIS_MODULE; > + chip->can_sleep = false; > + chip->base = -1; > + chip->direction_input = tqmx86_gpio_direction_input; > + chip->direction_output = tqmx86_gpio_direction_output; > + chip->get_direction = tqmx86_gpio_get_direction; > + chip->get = tqmx86_gpio_get; > + chip->set = tqmx86_gpio_set; So instead of these assignments just call bgpio_init() to get standard accessors. > + chip->ngpio = TQMX86_NGPIO; This will go away too as you send in that it's 8 bits wide. > + gpio->domain = irq_domain_add_linear(dev->of_node, 4, > + &irq_generic_chip_ops, > + gpio); > + if (!gpio->domain) > + return -ENOMEM; > + > + ret = irq_alloc_domain_generic_chips(gpio->domain, 4, 1, > + chip->label, > + handle_simple_irq, > + 0, 0, 0); > + if (ret) > + return ret; > + > + gc = gpio->domain->gc->gc[0]; > + gc->private = gpio; > + gc->chip_types[0].chip.irq_ack = tqmx86_gpio_irq_noop; > + gc->chip_types[0].chip.irq_mask = tqmx86_gpio_irq_mask; > + gc->chip_types[0].chip.irq_unmask = tqmx86_gpio_irq_unmask; > + gc->chip_types[0].chip.irq_set_type = tqmx86_gpio_irq_set_type; > + > + chip->to_irq = tqmx86_gpio_to_irq; As all this complex logic goes away with GPIOLIB_IRQCHIP I recommend you use that if you can. Since the struct gpio_irq_chip contains a "valid_mask" you can (hopefully) just mask off the 4 first IRQs as invalid and still use offsets 0..n for this GPIO irqchip. > + ret = gpiochip_add_data(chip, gpio); Why not devm_gpiochip_add_data()? > + gpiochip_remove(&gpio->chip); Then you don't need this. Yours, Linus Walleij
> Becuase I think this driver can use these two abstractions > quite nicely. It will diet the driver down to a very few > lines of code, which is nice. I am almost 100% sure that > you can use GPIO_GENERIC and 80% sure you can > use GPIOLIB_IRQCHIP. > > > +#define TQMX86_NGPIO 8 > > +#define TQMX86_DIR_MASK 0xf0 /* 0-3 - output, 4-7 - input */ > > +#define TQMX86_GPIODD 0 /* GPIO Data Direction Register */ > > +#define TQMX86_GPIOD 1 /* GPIO Data Register */ > > +#define TQMX86_GPIIC 3 /* GPI Interrupt Configuration Register */ > > +#define TQMX86_GPIIS 4 /* GPI Interrupt Status Register */ > > This looks like a very straight-forward MMIO GPIO Hi Linus I will look at GPIO_GENERIC, but these are not MMIO, registers, but Intel IO registered, using inb() and outb(). > > +static int tqmx86_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) > (...) > > + if (offset < 4 || offset > 7) > > + return -EINVAL; > > + ret = irq_create_mapping(gpio->domain, offset - 4); > > + if (ret > 0) > > + gpio->irqs[offset - 4] = ret; > > This "offset of 4" is something I don't quite get and would stop > you from using GPIOLIB_IRQCHIP. The device has 4 GPO and 4 GPI. Only the GPI can generate interrupts. > > +static void tqmx86_gpio_irq_mask(struct irq_data *data) > > +{ > > + struct tqmx86_gpio_data *gpio = data->domain->host_data; > > + unsigned long flags, irq_mask = data->mask; > > + int i; > > + u8 gpiic, mask = 0; > > + > > + for_each_set_bit(i, &irq_mask, 4) > > + mask |= 3 << (2 * i); > > This looks strange, can we have some comment explaining what > happens here? Something like two bits per IRQ I get it, > but how are the bits arranged in the register? Humm, i will have to reverse enginner this. I don't have a datasheet, just the vendor code. > > +static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) > > +{ > > + struct tqmx86_gpio_data *gpio = data->domain->host_data; > > + unsigned int edge_type = type & IRQF_TRIGGER_MASK; > > + unsigned int offset = data->hwirq * 2; /* 2 bits per line */ > > + unsigned long flags; > > + u8 new_type, gpiic; > > + > > + if (edge_type == IRQ_TYPE_EDGE_RISING) > > + new_type = TQMX86_GPII_RISING; > > + else if (edge_type == IRQ_TYPE_EDGE_FALLING) > > + new_type = TQMX86_GPII_FALLING; > > + else > > + return -EINVAL; /* not supported */ > > + > > + gpio->irq_type[offset] = new_type; > > So it doesn't support both egdes at the same time? > Since they appear to be two different bits it seems > like it can? I don't actually know. I also don't know if i have a way to test this, with the hardware i have. I've not yet even tested interrupts, they are not too important for my use case. Thanks for the comment Andrew
On Sun, Dec 09, 2018 at 12:01:52PM +0100, Linus Walleij wrote: > Hi Andrew! Thanks for your patch! > > On Sat, Dec 8, 2018 at 5:18 PM Andrew Lunn <andrew@lunn.ch> wrote: > > > Some TQ-Systems ComExpress modules contain an IO controller with 8 > > GPIO lines. > > > > Signed-off-by: Andrew Lunn <andrew@lunn.ch> > > > +config GPIO_TQMX86 > > + tristate "TQ-Systems QTMX86 GPIO" > > + depends on MFD_TQMX86 > > + select GENERIC_IRQ_CHIP > > I'd say probably remove that and add: > > select GPIO_GENERIC Hi Linus I've been looking at the generic code. As far as i can see, it does not work for this device. I see two problems: 1) This is not a mmio device, it is an ioport device. None of the accessors available in bgpio_setup_accessors() will work. 2) There does not appear to support the concept of some pins being GPO and some being GPI. If the problem was just 1), i could probably add the needed accessors, and add a new flag, to indicate ioport, not mmio. But handling the mix of GPI and GPO does not look too easy. Do you agree? Thanks Andrew
On Sun, Dec 9, 2018 at 9:54 PM Andrew Lunn <andrew@lunn.ch> wrote: > On Sun, Dec 09, 2018 at 12:01:52PM +0100, Linus Walleij wrote: > > Hi Andrew! Thanks for your patch! > > > > On Sat, Dec 8, 2018 at 5:18 PM Andrew Lunn <andrew@lunn.ch> wrote: > > > > > Some TQ-Systems ComExpress modules contain an IO controller with 8 > > > GPIO lines. > > > > > > Signed-off-by: Andrew Lunn <andrew@lunn.ch> > > > > > +config GPIO_TQMX86 > > > + tristate "TQ-Systems QTMX86 GPIO" > > > + depends on MFD_TQMX86 > > > + select GENERIC_IRQ_CHIP > > > > I'd say probably remove that and add: > > > > select GPIO_GENERIC > > Hi Linus > > I've been looking at the generic code. As far as i can see, it does > not work for this device. I see two problems: > > 1) This is not a mmio device, it is an ioport device. None of the > accessors available in bgpio_setup_accessors() will work. > > 2) There does not appear to support the concept of some pins being GPO > and some being GPI. > > If the problem was just 1), i could probably add the needed accessors, > and add a new flag, to indicate ioport, not mmio. But handling the mix > of GPI and GPO does not look too easy. > > Do you agree? Hm how typical, I see. I wanted to add port-mapped I/O to the gpio-mmio driver for some time but in this case it might not be worth it. I was confused because gpio-mmio uses some ioread/iowrite accessors which I guess simply translates into inb/outb on intel but readb/writeb on other architectures. I guess keep with the custom code. It'd be great if you could use GPIOLIB_IRQCHIP with a .valid_mask masking off the out-only GPIOs though, the centralized IRQ code is pretty helpful. Yours, Linus Walleij
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 833a1b51c948..74f37abf9017 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1168,6 +1168,13 @@ config GPIO_TPS68470 of the TPS68470 must be available before dependent drivers are loaded. +config GPIO_TQMX86 + tristate "TQ-Systems QTMX86 GPIO" + depends on MFD_TQMX86 + select GENERIC_IRQ_CHIP + help + This driver supports GPIO on the TQMX86 IO controller. + config GPIO_TWL4030 tristate "TWL4030, TWL5030, and TPS659x0 GPIOs" depends on TWL4030_CORE diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 671c4477c951..00ba709aeb6a 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -133,6 +133,7 @@ obj-$(CONFIG_GPIO_TPS6586X) += gpio-tps6586x.o obj-$(CONFIG_GPIO_TPS65910) += gpio-tps65910.o obj-$(CONFIG_GPIO_TPS65912) += gpio-tps65912.o obj-$(CONFIG_GPIO_TPS68470) += gpio-tps68470.o +obj-$(CONFIG_GPIO_TQMX86) += gpio-tqmx86.o obj-$(CONFIG_GPIO_TS4800) += gpio-ts4800.o obj-$(CONFIG_GPIO_TS4900) += gpio-ts4900.o obj-$(CONFIG_GPIO_TS5500) += gpio-ts5500.o diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c new file mode 100644 index 000000000000..146415f61b15 --- /dev/null +++ b/drivers/gpio/gpio-tqmx86.c @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TQ-Systems TQMx86 PLD GPIO driver + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/bitops.h> +#include <linux/errno.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/irq.h> +#include <linux/irqdomain.h> +#include <linux/interrupt.h> + +#define TQMX86_NGPIO 8 +#define TQMX86_DIR_MASK 0xf0 /* 0-3 - output, 4-7 - input */ +#define TQMX86_GPIODD 0 /* GPIO Data Direction Register */ +#define TQMX86_GPIOD 1 /* GPIO Data Register */ +#define TQMX86_GPIIC 3 /* GPI Interrupt Configuration Register */ +#define TQMX86_GPIIS 4 /* GPI Interrupt Status Register */ + +#define TQMX86_GPII_RISING 2 +#define TQMX86_GPII_FALLING 1 + +struct tqmx86_gpio_data { + struct gpio_chip chip; + void __iomem *io_base; + struct irq_domain *domain; + int irq; + spinlock_t spinlock; + u8 irq_type[4]; + int irqs[4]; /* mapped irqs */ +}; + +static u8 tqmx86_gpio_read(struct tqmx86_gpio_data *gd, unsigned int reg) +{ + return ioread8(gd->io_base + reg); +} + +static void tqmx86_gpio_write(struct tqmx86_gpio_data *gd, u8 val, + unsigned int reg) +{ + iowrite8(val, gd->io_base + reg); +} + +static int tqmx86_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip); + + return !!(tqmx86_gpio_read(gpio, TQMX86_GPIOD) & (1 << offset)); +} + +static void tqmx86_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + u8 val; + unsigned long flags; + struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip); + + spin_lock_irqsave(&gpio->spinlock, flags); + val = tqmx86_gpio_read(gpio, TQMX86_GPIOD); + if (value) + val |= 1 << offset; + else + val &= ~(1 << offset); + tqmx86_gpio_write(gpio, val, TQMX86_GPIOD); + spin_unlock_irqrestore(&gpio->spinlock, flags); +} + +static int tqmx86_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + /* Direction cannot be changed */ + if ((1 << offset) & TQMX86_DIR_MASK) + return 0; + else + return -EINVAL; +} + +static int tqmx86_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, + int value) +{ + /* Direction cannot be changed */ + if (((1 << offset) & TQMX86_DIR_MASK) == 0) + return 0; + else + return -EINVAL; +} + +static int tqmx86_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + return !!(TQMX86_DIR_MASK & (1 << offset)); +} + +static int tqmx86_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) +{ + struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip); + int ret; + + if (offset < 4 || offset > 7) + return -EINVAL; + ret = irq_create_mapping(gpio->domain, offset - 4); + if (ret > 0) + gpio->irqs[offset - 4] = ret; + + return ret; +} + +static void tqmx86_gpio_irq_noop(struct irq_data *data) +{ +} + +static void tqmx86_gpio_irq_mask(struct irq_data *data) +{ + struct tqmx86_gpio_data *gpio = data->domain->host_data; + unsigned long flags, irq_mask = data->mask; + int i; + u8 gpiic, mask = 0; + + for_each_set_bit(i, &irq_mask, 4) + mask |= 3 << (2 * i); + + if (mask) { + spin_lock_irqsave(&gpio->spinlock, flags); + gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); + gpiic &= ~mask; + tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC); + spin_unlock_irqrestore(&gpio->spinlock, flags); + } +} + +static void tqmx86_gpio_irq_unmask(struct irq_data *data) +{ + struct tqmx86_gpio_data *gpio = data->domain->host_data; + unsigned long flags, irq_mask = data->mask; + int i; + u8 gpiic, mask = 0; + + for_each_set_bit(i, &irq_mask, 4) + mask |= gpio->irq_type[i] << (2 * i); + + if (mask) { + spin_lock_irqsave(&gpio->spinlock, flags); + gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); + gpiic |= mask; + tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC); + spin_unlock_irqrestore(&gpio->spinlock, flags); + } +} + +static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) +{ + struct tqmx86_gpio_data *gpio = data->domain->host_data; + unsigned int edge_type = type & IRQF_TRIGGER_MASK; + unsigned int offset = data->hwirq * 2; /* 2 bits per line */ + unsigned long flags; + u8 new_type, gpiic; + + if (edge_type == IRQ_TYPE_EDGE_RISING) + new_type = TQMX86_GPII_RISING; + else if (edge_type == IRQ_TYPE_EDGE_FALLING) + new_type = TQMX86_GPII_FALLING; + else + return -EINVAL; /* not supported */ + + gpio->irq_type[offset] = new_type; + + spin_lock_irqsave(&gpio->spinlock, flags); + gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); + gpiic &= ~(3 << offset); + gpiic |= new_type << offset; + tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC); + spin_unlock_irqrestore(&gpio->spinlock, flags); + /* TODO: find offset, set GPIIC */ + + irqd_set_trigger_type(data, type); + + return IRQ_SET_MASK_OK; +} + +static irqreturn_t tqmx86_gpio_irq_cascade(int irq, void *data) +{ + struct tqmx86_gpio_data *gpio = data; + u8 irq_status = tqmx86_gpio_read(gpio, TQMX86_GPIIS); + int i; + unsigned long irq_bits; + + if (!irq_status) + return IRQ_HANDLED; + + tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS); + + irq_bits = irq_status; + for_each_set_bit(i, &irq_bits, 4) + generic_handle_irq(irq_find_mapping(gpio->domain, i)); + + return IRQ_HANDLED; +} + +static int tqmx86_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct tqmx86_gpio_data *gpio; + struct gpio_chip *chip; + struct resource *res; + void __iomem *io_base; + int ret; + int irq; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + res = platform_get_resource(pdev, IORESOURCE_IO, 0); + if (IS_ERR(res)) { + dev_err(&pdev->dev, "Cannot get I/O\n"); + return PTR_ERR(res); + } + io_base = devm_ioport_map(&pdev->dev, res->start, resource_size(res)); + if (IS_ERR(io_base)) + return PTR_ERR(io_base); + + gpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL); + if (gpio == NULL) + return -ENOMEM; + + spin_lock_init(&gpio->spinlock); + gpio->io_base = io_base; + + tqmx86_gpio_write(gpio, (u8)~TQMX86_DIR_MASK, TQMX86_GPIODD); + + platform_set_drvdata(pdev, gpio); + + chip = &gpio->chip; + chip->label = "gpio-tqmx86"; + chip->owner = THIS_MODULE; + chip->can_sleep = false; + chip->base = -1; + chip->direction_input = tqmx86_gpio_direction_input; + chip->direction_output = tqmx86_gpio_direction_output; + chip->get_direction = tqmx86_gpio_get_direction; + chip->get = tqmx86_gpio_get; + chip->set = tqmx86_gpio_set; + chip->ngpio = TQMX86_NGPIO; + + if (irq) { + struct irq_chip_generic *gc; + + ret = devm_request_irq(dev, irq, tqmx86_gpio_irq_cascade, + IRQF_TRIGGER_NONE, + dev_name(dev), gpio); + + if (ret != 0) { + dev_err(dev, "Can't request irq.\n"); + return ret; + } + + gpio->domain = irq_domain_add_linear(dev->of_node, 4, + &irq_generic_chip_ops, + gpio); + if (!gpio->domain) + return -ENOMEM; + + ret = irq_alloc_domain_generic_chips(gpio->domain, 4, 1, + chip->label, + handle_simple_irq, + 0, 0, 0); + if (ret) + return ret; + + gc = gpio->domain->gc->gc[0]; + gc->private = gpio; + gc->chip_types[0].chip.irq_ack = tqmx86_gpio_irq_noop; + gc->chip_types[0].chip.irq_mask = tqmx86_gpio_irq_mask; + gc->chip_types[0].chip.irq_unmask = tqmx86_gpio_irq_unmask; + gc->chip_types[0].chip.irq_set_type = tqmx86_gpio_irq_set_type; + + chip->to_irq = tqmx86_gpio_to_irq; + } + + ret = gpiochip_add_data(chip, gpio); + if (ret) { + dev_err(dev, "Could not register GPIO chip\n"); + return ret; + } + + dev_info(dev, "GPIO functionality initialized with %d pins\n", + chip->ngpio); + + return 0; +} + +static int tqmx86_gpio_remove(struct platform_device *pdev) +{ + struct tqmx86_gpio_data *gpio = platform_get_drvdata(pdev); + int i; + + if (gpio->chip.to_irq) { + for (i = 0; i < 4; i++) { + if (gpio->irqs[i]) + irq_dispose_mapping(gpio->irqs[i]); + } + kfree(gpio->domain->gc); + irq_domain_remove(gpio->domain); + } + gpiochip_remove(&gpio->chip); + return 0; +} + +static struct platform_driver tqmx86_gpio_driver = { + .driver = { + .name = "tqmx86-gpio", + }, + .probe = tqmx86_gpio_probe, + .remove = tqmx86_gpio_remove, +}; + +module_platform_driver(tqmx86_gpio_driver); + +MODULE_DESCRIPTION("TQMx86 PLD GPIO Driver"); +MODULE_AUTHOR("Vadim V.Vlasov <vvlasov@dev.rtsoft.ru>"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:tqmx86-gpio");
Some TQ-Systems ComExpress modules contain an IO controller with 8 GPIO lines. Signed-off-by: Andrew Lunn <andrew@lunn.ch> --- drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-tqmx86.c | 333 +++++++++++++++++++++++++++++++++++++ 3 files changed, 341 insertions(+) create mode 100644 drivers/gpio/gpio-tqmx86.c